Qspi; Uarts - Quectel FCM561D-P Hardware Design

3.4.2. QSPI

In the case of multiplexing, the module embeds 1 Quad SPI that provides support for communicating
with external flash, PSRAM or AMOLED display. The QSPI allows maximum clock frequency up to
80 MHz.
Table 8: Pin Definition of QSPI
Pin Name Pin No.
GPIO22 28
GPIO23 27
GPIO24 72
GPIO25 71
GPIO26 70
GPIO27 11
The following figure shows the QSPI connection between the host and the slave:

3.4.3. UARTs

The module provides 3 UARTs, among which UART1 is default configuration while UART2 and UART3
are multiplexed with GPIOs. The interfaces support full-duplex asynchronous serial communication at a
baud rate up to 2 Mbps. UART1 supports hardware flow control with RTS and CTS signals, flash
download and debugging information output. Each UART embeds a 128-byte Tx FIFO and a 128-byte
Rx FIFO. FIFO mode is disabled by default and can be enabled by software.
FCM561D-P_Hardware_Design
Multiplexing Function
QSPI_CLK
QSPI_CS
QSPI_DATA0
QSPI_DATA1
QSPI_DATA2
QSPI_DATA3
QSPI_CS
QSPI_CLK
QSPI_DATA[0:3]
QSPI (Host)
Figure 3: QSPI Connection
Wi-Fi&Bluetooth Module Series
I/O Description
DIO QSPI clock
DIO QSPI chip select
DIO QSPI data bit 0
DIO QSPI data bit 1
DIO QSPI data bit 2
DIO QSPI data bit 3
QSPI_CS
QSPI_CLK
QSPI_DATA[0:3]
QSPI (Slave)
24 / 65