Quectel FCM561D-P Hardware Design page 27

Table 10: Pin Definition of SDIO Interface
Pin Name Pin No.
GPIO2 21
GPIO3 20
GPIO4 19
GPIO5 18
GPIO10 37
GPIO11 38
The following figure shows the SDIO interface connection between the module and the host:
SDIO_CLK
SDIO_CMD
SDIO_DATA0
SDIO_DATA1
SDIO_DATA2
SDIO_DATA3
Module
To ensure compliance of interface design with the SDIO 2.0 specification, it is recommended to adopt
the following principles:
⚫
Route the SDIO traces in inner layer of the PCB, and surround the traces with ground on that layer
and with ground planes above and below. The impedance of SDIO signal trace is 50 Ω ±10 %.
⚫
Keep SDIO signals far away from other sensitive circuits/signals such as RF circuits and analog
FCM561D-P_Hardware_Design
Multiplexing Function
SDIO_CLK
SDIO_CMD
SDIO_DATA0
SDIO_DATA1
SDIO_DATA2
SDIO_DATA3
Figure 5: SDIO Interface Connection
Wi-Fi&Bluetooth Module Series
I/O Description
DIO SDIO clock
DIO SDIO command
DIO SDIO data bit 0
DIO SDIO data bit 1
DIO SDIO data bit 2
DIO SDIO data bit 3
SDIO_CLK
SDIO_CMD
SDIO_DATA0
SDIO_DATA1
SDIO_DATA2
SDIO_DATA3
Comment
Other SDIO
configurations,
see Table 6.
VBAT
Host
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