Application Interfaces; Spis - Quectel FCM561D-P Hardware Design

3.4. Application Interfaces

3.4.1. SPIs

In the case of multiplexing, the module integrates 2 SPIs that can operate in master or slave mode with
maximum clock frequency of 30 MHz. The SPIs support 8-bit or 16-bit data width and 4-wire or 3-wire
(without CS pin) mode.
Table 7: Pin Definition of SPIs
Pin Name Pin No.
GPIO14 61
GPIO16 63
GPIO15 62
GPIO17 64
GPIO2 21
GPIO3 20
GPIO4 19
GPIO5 18
The following figure shows the connection between the host and the slave:
FCM561D-P_Hardware_Design
Multiplexing Function
SPI1_CLK
SPI1_CS
SPI1_MOSI
SPI1_MISO
SPI2_CLK
SPI2_CS
SPI2_MOSI
SPI2_MISO
SPI_CS
SPI_CLK
SPI_MOSI
SPI_MISO
SPI (Host)
Figure 2: SPI Connection
Wi-Fi&Bluetooth Module Series
I/O Description
DIO SPI1 clock
DIO SPI1 chip select
DIO SPI1 master-out slave-in
DIO SPI1 master-in slave-out
DIO SPI2 clock
DIO SPI2 chip select
DIO SPI2 master-out slave-in
DIO SPI2 master-in slave-out
SPI_CS
SPI_CLK
SPI_MOSI
SPI_MISO
SPI (Slave)
Comment
Other SPI1
configurations,
see Table 6.
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