Camera Interface - Quectel FCM561D-P Hardware Design

GPIO43 34
GPIO44 33
GPIO45 32
GPIO46 67
GPIO47 66

3.4.9. Camera Interface

In the case of multiplexing, the module supports 1 camera interface. The 8-bit CMOS Image Sensor (CIS)
Digital Video Port (DVP) camera interface provides 8-bit parallel port interface to sensors, together with
main clock (MCLK), pixel clock (PCLK), horizontal SYNC (HSYNC) and vertical SYNC (VSYNC) signals.
The YUV sensor's input will be directly fed to the hardware JPEG encoder, and the JPEG encoder output
is written to data memory directly by a dedicated DMA channel. The YUV signal format could be YUYV,
UYVY, YYUV and UVYY. HSYNC and VSYNC level could be set independently.
Table 16: Pin Definition of Camera DVP Interface
Pin Name Pin No.
GPIO27 11
GPIO29 55
GPIO30 56
GPIO31 57
GPIO32 53
GPIO33 52
GPIO34 54
GPIO35 12
GPIO36 13
GPIO37 14
GPIO38 16
FCM561D-P_Hardware_Design
LCD_DATA4
LCD_DATA3
LCD_DATA2
LCD_DATA1
LCD_DATA0
Multiplexing Function
DVP_MCLK
DVP_PCLK
DVP_HSYNC
DVP_VSYNC
DVP_DATA0
DVP_DATA1
DVP_DATA2
DVP_DATA3
DVP_DATA4
DVP_DATA5
DVP_DATA6
Wi-Fi&Bluetooth Module Series
DIO I8080 data bit 4
DIO I8080 data bit 3
DIO I8080 data bit 2
DIO I8080 data bit 1
DIO I8080 data bit 0
I/O Description
DO DVP master clock
DO DVP pixel clock
DO DVP horizontal sync
DO DVP vertical sync
DIO DVP data bit 0
DIO DVP data bit 1
DIO DVP data bit 2
DIO DVP data bit 3
DIO DVP data bit 4
DIO DVP data bit 5
DIO DVP data bit 6
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