Table of Contents
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– Debug mode
– Serial wire debug (SWD) & JTAG interfaces
– Cortex-M3 Embedded Trace Macrocell™
– 80 fast I/O ports
– 80 I/Os, all mappable on 16 external interrupt vectors and almost all 5 V-tolerant
– 10 timers
– four 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature
(incremental) encoder input
– 1 × 16-bit motor control PWM timer with dead-time generation and emergency stop
– 2 × watchdog timers (Independent and Window)
– SysTick timer: a 24-bit downcounter
– 2 × 16-bit basic timers to drive the DAC
– 14 communication interfaces
2
– 2 × I
C interfaces (SMBus/PMBus)
– 5 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control)
– 3 SPIs (18 Mbit/s), 2 with a multiplexed I
advanced PLL schemes
– 2 × CAN interfaces (2.0B Active) with 512 bytes of dedicated SRAM
– USB 2.0 full-speed device/host/OTG controller with on-chip PHY that supports
HNP/SRP/ID with 1.25 Kbytes of dedicated SRAM
– 10/100 Ethernet MAC with dedicated DMA and SRAM (4 Kbytes): IEEE1588 hardware
support, MII/RMII available on all packages
– CRC calculation unit, 96-bit unique ID
2
S interface that offers audio class accuracy via
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