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The disk drive is shipped with R50 in place and with R51 not in place. If the resistor is moved to position R51, the
power is only on to the stepper motor when the disk drive is selected. 3.8 watts of power are saved because
power is not applied to the stepper motor unless the disk drive is selected
.
3.3.1.4
Write Enable (N WRITE ENABLE)
Functional Description
When the Write Enable signal is true (low), the write electronics are prepared for writing data (read electronics
disabled). This signal turns on the write current in the read/write head. Data
is
written under control of the Write
Data input line. It is generally recommended that changes of state on the Write Enable line occur before the first
Write Data pulse. However, the separation between the leading edge of Write Enable and the first significant
Write Data pulse should not be less than four (4) usec and not greater than eight (8) usec. The same restrictions
exist for the relationship between the least significant Write Data pulse and the termination of the Write Enable
signal. When the Write Enable line is false (high), all write electronics are disabled.
When a write-protected diskette is installed in the disk
drive,
the write electronics are disabled,
irrespective
of the
state of the Write Enable line. Stepping is also disabled by a true (low) Write Enable (see Section 3.3.1.3).
Tandon Corporation recommends that the controller wait one (1) msec after the N WRITE ENABLE goes false
before any step pulses are sent to the disk drive.
Circuit Description
The Write Gate signal comes in on Pin 24 of the interface connector. It is buffered through IC 3D, and gated at IC
3B by the Write Protect and the Unit Select signals, becoming the N WRITE signal. The N WRITE signal goes to
Pin 9 of IC 3C, which is configured as a delay. The output at Pin 12 goes high 390 usec after the N WRITE signal
goes true.
The N WRITE signal also goes to IC 3C, Pin 1, which is configured as a one-shot
delay.
The output at Pin 13 goes
low only 900 usec after it stops getting pulses at Pin 2 (the pulse from the write data circuit), and the N WRITE
goes high or false.
The N ERASE signal
is
gated through IC 3B. It is true 390 usec after a write true and 900 usec after a write false.
This signal enables the erase driver IC 2C. R58 controls the erase current, which is approximately 80 mA.
Pin 4 of IC 3C is the Not Internal Write Busy signal. It enables 05 through IC 3E, and gates twelve (12) volts to the
selected head. This signal also disables the data output at IC SE, Pin 11
.
The Not Internal Write Busy signal also
enables the write flip flop IC SC through IC 2E, Pin 12 and Pin 13.
Finally, the Not Internal Write Busy signal goes to driver 2B, Pin 10 and Pin 11, to disable the signal from the
heads to the first-stage amplifier, using diodes CR11 and CR12 as gates.
3.3.1.5
Write Data (N WRITE DATA)
Functional Description
When the disk drive
is
selected, the write data line provides the bit-serial Write Data pulses that control the switch-
ing of the write current in the heads. The write electronics must be conditioned for writing by the Write Enable line
(see Section 3.3.1 .4).
For each high-to-low
transition
on the Write Data line, a flux change is produced at
the
head write gap. This
causes a flux change to be stored on the disk drive.
(See
Figure 3-6.)
When the double-frequency type encoding technique
is
used (in which data and clock form the combined Write
Data signal), it is recommended that the repetition of the high-to-low transitions, when writing all zeros, be equal
to the nominal data rate
±
0.1 percent. The
repetition
rate of the high-to-low transitions, when writing all ones,
should be equal to twice the nominal data rate
+
0.1 percent. The data transfer rate is 125,000 Bits Per Second
(BPS) at single density; it is 250,000 BPS at double density.
3-9
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