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3.3.1.3
Direction and Step Lines (Two Lines)
(DIR)
(N STEP)
Functional Description
When the disk drive is selected, a true (low) pulse with a time duration greater than 200 nsec on the Step line
initiates the access motion. The direction of motion is determined by the logic state of the Direction line when a
Step pulse is issued. The motion is toward the center of the disk drive if the Direction line is in the true (low) state
when a Step pulse is issued. The direction of motion
is
away from the center of the disk drive if the Direction line is
in
the false (high) state when a Step pulse is
issued.
To ensure proper positioning, the direction line should be
stable 100 usec (minimum) before the
trailing
edge of the corresponding Step pulse. The Direction line should re-
main stable until 100
usec
after the trailing edge of the Step pulse. The access motion is initiated on the trailing
edge of the Step pulse.
Test Point 8 (see Figure 3-5) is low (true) when the carriage is positioned at Track 00 and the step motor is at
Phase 0.
When stepping
in
or out,
Test
Point 12 (see Figure
3-5) is
a high going pulse for each step of the carriage
(see Table 3-4).
Step In (Toward Track 00)
Phase
Pin
No.
0
3
2
4C-5
0
1
1
4C-6
1
0
0
4C-9
0
0
1
4C-8
1
1
0
Circuit Description
TABLE 3-4
STEPPER LOGIC TRUTH
Step Out (Toward Track 40)
Phase
1
0
Pin No.
0
1
2
0
0
4C-5
0
0
1
1
1
4C-6
1
1
0
1
0
4C-9
0
1
1
0
1
4C-8
1
0
0
3
0
1
0
0
1
0
0
1
1
The direction line comes
in
on Pin 18 of
the
interface connector. A high signal directs the step logic to step in to-
ward Track 00. A low signal directs the stop logic to step out toward Track
39.
The direction line sets the proper phase
to
the exclusive OR gates of IC 5D. This signal is also buffered by IC 3D to
gate IC 4F to inhibit stepping
inward
when the disk drive is already at Track 00. This is done at Pin 4 of IC
48.
The step pulses come
in
at Pin 20 of the
interface
connector. They are buffered by 2E and gated at IC 48 by the
unit
select,
the Not Write signal, and by the inward step inhibit at the Track 00 signal. Then, the step pulses go to
the C inputs of the two (2) flip flops at
IC
4C. The direction of the step, hence the selection of the flip flop to be
toggled, is done by the two
(2)
exclusive OR gates of IC 5D
.
These gates are controlled by the step direction line
and by the state of the two (2) flip flop outputs.
IC
3E,
Pins 5 and
6,
resets the
two
(2)
flip flops after a Power On.
The output of
the
two
(2)
flip flops drives the stepper motor through the drivers of IC
4D.
The diodes are for voltage
spike elimination.
3-7
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