Seco Smarc CSM-B79 User Manual page 63

Signal description of I2S Audio Header CN81:
I2S2_SDIN_3.3V: I2S Digital Audio Input Signal, derived from SMARC
I2S2_SDOUT_3.3V: I2S Digital Audio Output Signal, derived from SMARC
I2S2_LRCLK_3.3V: I2S Left & Right Synchronization Clock, derived from SMARC
I2S2_RST#_3.3V: I2S Digital Audio Reset Output, active low signal. This signal is routed through 3-way jumper CN82, so the signal is derived by HDA_RST# (1-2
position) or by RESET_OUT# (2-3 position, default)
I2S2_CLK_3.3V: I2S Digital Audio Clock Signal, derived from SMARC
GP_I2C_DAT_3V3: General Purpose I2C I/O Data Signal, derived from SMARC
electrical level with 2k2 up resistor. Also carried to Feature Header CN45 (par.3.3.26)
GP_I2C_CLK_3V3: General Purpose I2C Clock Output Signal, derived from SMARC
CSM-B79
CSM-B79 User Manual - Rev. First Edition: 1.0 - Last Edition: 1.1 - Author: A.R - Reviewed by S.R. - Copyright © 2021 SECO S.p.A.
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Module I2S2_SDIN. +3V3_RUN electrical level
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Module I2S2_SDOUT. +3V3_RUN electrical level
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Module I2S2_CK. +3V3_RUN electrical level
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resistor. Also carried to Feature Header CN45 (par.3.3.26)
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Module I2S2_LRCK. +3V3_RUN electrical level
I2C_GP_DAT with a set of back to back FETs to voltage translate. +3.3V_RUN
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I2C_GP_CK with a set of back to back FETs to voltage translate.
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