Seco Smarc CSM-B79 User Manual page 36

Carrier board for smarc rel. 2.0 / 2.1 compliant modules
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LVDS1_D[0..3]+_CONN / LVDS1_D[0..3]-_CONN: SMARC
LVDS1_CLK+_CONN / LVDS1_CLK-_CONN: SMARC
LVDS_DDC_DAT_3V3: Display ID Data line for Flat Panel detection and control. Signal derived by I2C_LCD_DAT from SMARC
translator. Bidirectional signal, +3.3V_RUN electrical level with 2k2 pull up resistor
LVDS_DDC_CLK_3V3: Display ID Clock line for Flat Panel detection and control. Signal derived by I2C_LCD_CK from SMARC
translator. Bidirectional signal, +3.3V_RUN electrical level with 2k2 pull up resistor
LCD0_VDD_EN_3V3: LVDS Panel power for LCD Enable Signal, derived by LCD0_VDD_EN from SMARC
electrical level Output.
LCD0_BKLTEN_3V3: LVDS Panel power for Backlight Enable Signal, derived by LCD0_BKLT_EN from SMARC
electrical level Output.
LCD0_BKLT_PWM_3V3: LVDS Panel Backlight Brightness Control, PWM signal derived by LCD0_BKLT_PWM from SMARC
+3.3V_RUN electrical level Output.
SW6 position
LVDS / eDP selector
ON position (1-3)
eDP1
OFF position (1-3)
LVDS1 / DSI1
ON position (2-4)
eDP0
OFF position (2-4)
LVDS0 / DSI0
CN18 position
LCD #0 PWR selector (VDD_LCD0)
1-2
+3.3V_RUN
2-3
+5V_RUN
CN19 position
BKLT #0 PWR selector (VDD_BKLT0)
1-2
+12V_RUN
2-3
+5V_RUN
CSM-B79
CSM-B79 User Manual - Rev. First Edition: 1.0 - Last Edition: 1.1 - Author: A.R - Reviewed by S.R. - Copyright © 2021 SECO S.p.A.
®
Module LVDS Channel#1 Differential pairs
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Module LVDS Channel#1 Differential clock
In order to match the CSM-B79 Carrier Board with the primary display interfaces effectively available on the
®
SMARC
module, it is necessary to configure properly the dual DIP switch SW6, type ADIMPEX p/n KVT04602-
R, according to the left table.
In order to support Dual Channel LVDS configuration or MIPI-DSI dual channel, both DIP switches must be
placed in OFF positions.
The LCD Voltage rail VDD_LCD0 value can be set to +3.3V_RUN or +5V_RUN by using dedicated
jumper CN18, which is a standard pin header, P2.54mm, 1x3 pin.
This selectable power rail is carried both to LVDS connector CN14 and eDP0 connector
CN60 (par.3.3.3).
The Backlight Voltage rail VDD_BKLT0 value can be set to +5V_RUN or +12V_RUN by
using dedicated jumper CN19, which is another standard pin header, P2.54mm, 1x3 pin.
This selectable power rail is carried both to LVDS connector CN14 and eDP0 connector CN60
(par.3.3.3).
®
Module through voltage level
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Module through voltage level
®
Module through voltage level translator. +3.3V_RUN
®
Module through voltage level translator. +3.3V_RUN
®
Module through voltage level translator.
36

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