Seco Smarc CSM-B79 User Manual page 52

Carrier board for smarc rel. 2.0 / 2.1 compliant modules

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Table Of Contents

Table of Contents

Two 2-way jumpers allow forcing the W_DISABLEX#_E signals available on this socket

JP16 position

W_DISABLE1#_E

Not Inserted

WiFi enabled

Inserted

WiFi disabled

Signals carried to M.2 WLAN Slot are the following:

PCIe_B_Tx+_M2 / PCIe_B_Tx-_M2: SMARC

PCIe_B_Rx+_M2 / PCIe_B_Rx-_M2: SMARC

PCIe_B_CLK+_M2 / PCIe_B_CLK-_M2: SMARC

USB4+ / USB4-: SMARC

module USB Port #4 differential pair

PCIe_WAKE#

Input, it must be externally driven by the M.2 WLAN module inserted in the slot when it requires waking up the system. This signal is

connected directly to SMARC

PCIe_B_RST#: WLAN specific reset Active Low Output Signal, directly driven by the SMARC

PCIE_B_CLKREQ#: PCI Express Clock Request Input for lane #B. This signal shall be driven low by the module inserted in the M.2 WLAN slot, in order to ensure

that the PCI Express Reference Clock for lane #B is made available for this slot (i.e. PCIe_B_CLK+_M2 / PCIe_B_CLK-_M2)

W_DISABLE1_E#: this signal can be used to enable/disable the WiFi functionality of a M.2 WLAN module plugged in slot CN36. This signal is directly managed using

jumper JP16 as described in the table below

W_DISABLE2_E#: this signal can be used to enable/disable the BT functionality of a M.2 WLAN module plugged in slot CN36. This signal is directly managed using

jumper JP15, as described in the table below

LED_1#: Indicator Output Signal driven low by the module inserted in the M.2 WLAN slot, used to activate LED diode D97 on CSM-B79 carrier board, signalling,

when LED is ON, correct working of Wi-Fi functionality

LED_2#: Indicator Output Signal driven low by the module inserted in the M.2 WLAN slot, used to activate LED diode D98 on CSM-B79 carrier board, signalling,

when LED is ON, correct working of BT functionality

CSM-B79

JP15 position

W_DISABLE2#_E

Not Inserted

BT enabled

Inserted

BT disabled

module PCI Express lane #B, Transmitting Output Differential pair

module PCI Express lane #B, Receiving Input Differential pair

module PCI Express Reference Clock for lane #B, Differential Pair

PCIE_WAKE# signal