Power-On/Off Sequences; Figure 3. Power-On Sequence; Figure 4. Power-Off Sequence - ST Sound Terminal STA333W Manual

Electrical specification
3.5

Power-on/off sequences

The power-on/off sequences shown in
on and turn off.
Figure 3.
VCC VCC
VCC
VDD_Dig VDD_Dig
VDD_DIG
XTI XTI
XTI
Reset Reset
RESET
PWRDN PWRDN PWRDN
Bit EAPD
Soft EAPD Soft EAPD
Register 0x05
Reg. 0x05 Reg. 0x05
Bit 7 = 1 Bit 7 = 1
Figure 4.
VCC
VCC VCC
VDD_DIG
VDD_Dig VDD_Dig
XTI
XTI XTI
Soft Mute Soft Mute Mute
Register 0x07
Reg. 0x07 Reg. 0x07
Data 0xFE Data 0xFE
Bit EAPD
Soft EAPD Soft EAPD
Register 0x05
Reg. 0x05 Reg. 0x05
Bit 7 = 0 Bit 7 = 0
14/49
Power-on sequence
Don't care Don't care
Don't care Don't care Don't care Don't care
TR = mimimum time between XTI master clock stable and reset removal: 1 ms
TC = minimum time between reset removal and I
Clock stable means: fmax - fmin < 1 MHz
Power-off sequence
Don't care Don't care
Doc ID 13365 Rev 2
Figure 3 and Figure 4
No specific VCC and VDD_DIG turn-on sequence is required
TR TR
2
C program sequence start: 1 ms
No specific VCC and VDD_DIG turn-off sequence is required
FE FE
below ensure a pop-free turn
TC TC
Don't care Don't care
Don't care Don't care Don't care Don't care
Don't care Don't care
STA333W