User Manuals: ST 8542310000 8-bit Microcontrollers

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ST 8542310000 Manual (49 pages)

2-channel high-efficiency digital audio system

Brand: ST | Category: Microcontrollers | Size: 1 MB

Table 1. Device Summary
1
Table of Contents
2
Block Diagram
7
Figure 1. Block Diagram
7
Pin Description
8
Pin out
8
Pin List
8
Table 2
8
Figure 2. Pin Connection (Package Top View)
8
Table 2
9
Thermal Data
10
Table 3. Thermal Data
10
Electrical Specification
11
Absolute Maximum Ratings
11
Recommended Operating Conditions
11
Table 4. Absolute Maximum Ratings
11
Table 5. Recommended Operating Conditions
11
Electrical Specifications - Digital Section
12
Electrical Specifications - Power Section
12
Table 6. Electrical Characteristics for Digital Section
12
Power-On/Off Sequences
14
Figure 3. Power-On Sequence
14
Figure 4. Power-Off Sequence
14
Testing
15
Figure 5. Test Circuit
15
Figure 6. Current Dead-Time Test Circuit
15
Functional Description
16
Functional Pins
16
Power-Down Function
16
Reset Function
16
Serial Audio Interface Description
17
Serial Audio Interface Protocols
17
Figure 8. Left Justified
17
I 2 C Bus Specification
18
Communication Protocol
18
Data Transition or Change
18
Start Condition
18
Stop Condition
18
Data Input
18
Device Addressing
18
Write Operation
19
Byte Write
19
Multi-Byte Write
19
Read Operation
19
Current Address Byte Read
19
Current Address Multi-Byte Read
19
Random Address Byte Read
19
Figure 9. Write-Mode Sequence
19
Random Address Multi-Byte Read
20
Figure 10. Read-Mode Sequence
20
Register Description
21
Register Summary
21
Configuration Registers (Addr 0X00 to 0X05)
22
Configuration Register a (Addr 0X00)
22
Table 9. Master Clock Select
22
Table 10. MCS Bits
22
Table 11. Interpolation Ratio Select
23
Table 12. IR Bit Settings as a Function of Input Sample Rate
23
Table 13. Thermal Warning Recovery
23
Configuration Register B (Addr 0X01)
24
Table 14. Thermal Warning Adjustment
24
Table 15. Fault Detect Recovery
24
Table 16. Serial Audio Input Interface Format
25
Table 17. Serial Data First Bit
25
Table 19. Supported Serial Audio Input Formats for LSB-First (SAIFB = 1)
26
Configuration Register C (Addr 0X02)
27
Table 20. Channel Input Mapping
27
Table 21. DDX Power Output Mode
27
Table 22. DDX Compensating Pulse Size
27
Configuration Register D (Addr 0X03)
28
Configuration Register E (Addr 0X04)
28
Table 23. Overcurrent Warning Detect Adjustment Bypass
28
Table 24. Zero Detect Mute Enable
28
Table 25. Max Power Correction Variable
28
Table 26. Max Power Correction
29
Table 27. Noise-Shaper Bandwidth Selection
29
Table 28. am Mode Enable
29
Table 29. PWM Speed Mode
29
Table 30. Distortion Compensation Variable Enable
29
Configuration Register F (Addr 0X05)
30
Table 31. Zero-Crossing Volume Enable
30
Table 32. Zero-Crossing Volume Enable
30
Table 33. Invalid Input Detect Mute Enable
30
Table 34. Binary Output Mode Clock Loss Detection
30
Table 35. LRCK Double Trigger Protection
31
Table 36. Auto EAPD on Clock Loss
31
Table 37. Power down
31
Table 38. External Amplifier Power down
31
Volume Control Registers (Addr 0X06 to 0X09)
32
Mute/Line Output Configuration Register (Addr 0X06)
32
Table 39. Master Mute
32
Table 40. Channel Mute
32
Master Volume Register (Addr 0X07)
33
Channel Volume (Addr 0X08, 0X09)
33
Table 41. Master Volume Offset as a Function of MV
33
Automodes™ Register (0X0C)
34
Table 42. Channel Volume as a Function of CXV
34
Table 43. am Interference Frequency Switching
34
Table 44. Automodes™ am Switching Frequency Selection
34
Channel Configuration Registers (Addr 0X0E, 0X0F)
35
Variable Max Power Correction Registers (Addr 0X27, 0X28)
35
Variable Distortion Compensation Registers (Addr 0X29, 0X2A)
36
Fault Detect Recovery Constant Registers (Addr 0X2B, 0X2C)
36
Device Status Register (Addr 0X2D)
36
Table 45. Status Bits Description
36
Reserved Registers (Addr 0X2E, 0X2F, 0X30, 0X31)
37
Postscale Registers (Addr 0X32, 0X33)
37
Output Limit Register (Addr 0X34)
38
Thermal and Overcurrent Warning Output Limit Register
38
Table 46. Output Limit Values for Thermal and Overcurrent Warnings
38
Applications Information
39
Applications Scheme for Power Supplies
39
PLL Filter
39
Figure 11. Applications Diagram
39
Typical Output Configuration
40
Figure 12. PLL Filter Circuit
40
Figure 13. Output Configuration for Stereo BTL Mode
40
Characterization Data
41
Figure 14. Output Power Vs. Supply Voltage (THD = 1%)
41
Figure 15. FFT 0 Dbfs (VCC = 12 V)
41
Figure 16. FFT -60 Dbfs (VCC = 12 V)
42
Figure 17. THD Vs. Frequency (VCC = 12 V, Po = 1 W)
42
Figure 18. FFT 0 Dbfs (VCC = 18 V)
43
Figure 19. FFT -60 Dbfs (VCC = 18 V)
43
Figure 20. THD Vs. Frequency (VCC = 18 V, Po = 1 W)
43
Package Thermal Characteristics
44
Figure 21. Double-Layer PCB with Two Copper Ground Areas and 16 Vias
44
Figure 22. Power Derating Curve for PCB Used as Heatsink
44
Figure 23. Powersso-36 EPD Outline Drawing
45
Table 47. Table
48

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