Supermicro 8042-6 User Manual page 109

Supermicro superserver 8042-6 servers: user guide
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Checkpoint
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
A2h
A3h
A4h
A5h
A7h
A8h
A9h
Aah
Abh
B0h
B1h
00h
Code Description
Initializing the bus option ROMs from C800 next. See the last page of
this chapter for additional information.
Initializing before passing control to the adaptor ROM at C800.
Initialization before the C800 adaptor ROM gains control has com
pleted. The adaptor ROM check is next.
The adaptor ROM had control and has now returned control to BIOS
POST. Performing any required processing after the option ROM
returned control.
Any initialization required after the option ROM test has completed.
Configuring the timer data area and printer base address next.
Set the timer and printer base addresses. Setting the RS-232 base
address next.
Returned after setting the RS-232 base address. Performing any
required initialization before the Coprocessor test next.
Required initialization before the Coprocessor test is over. Initializing
the Coprocessor next.
Coprocessor initialized. Performing any required initialization after
the Coprocessor test next.
Initialization after the Coprocessor test is complete. Checking the
extended keyboard, keyboard ID, and Num Lock key next. Issuing the
keyboard ID command next.
Displaying any soft errors next.
The soft error display has completed. Setting the keyboard typematic
rate next.
The keyboard typematic rate is set. Programming the memory wait
states next.
Memory wait state programming is over. Clearing the screen and
enabling parity and the NMI next.
NMI and parity enabled. Performing any initialization required before
passing control to the adaptor ROM at E000 next.
Initialization before passing control to the adaptor ROM at E000h
completed. Passing control to the adaptor ROM at E000h next.
Returned from adaptor ROM at E000h control. Performing any
initialization required after the E000 option ROM had control next.
Initialization after E000 option ROM control has completed. Displaying
the system configuration next.
Uncompressing the DMI data and executing DMI POST initialization
next.
The system configuration is displayed.
Copying any code to specific areas.
Code copying to specific areas is done. Passing control to INT 19h
boot loader next.
Appendix B: BIOS POST Checkpoint Codes
B-7

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