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Checkpoint
48h
49h
4Bh
4Ch
4Dh
4Eh
4Fh
50h
51h
52h
53h
54h
57h
58h
59h
Code Description
Patterns written in base memory. Determining the amount of memory
below 1 MB next.
The amount of memory below 1 MB has been found and verified.
Determining the amount of memory above 1 MB memory next.
The amount of memory above 1 MB has been found and verified.
Checking for a soft reset and clearing the memory below 1 MB for
the soft reset next. If this is a power on situation, going to checkpoint
4Eh next.
The memory below 1 MB has been cleared via a soft reset. Clearing
the memory above 1 MB next.
The memory above 1 MB has been cleared via a soft reset. Saving
the memory size next. Going to checkpoint 52h next.
The memory test started, but not as the result of a soft reset.
Displaying the first 64 KB memory size next.
The memory size display has started. The display is updated during
the memory test. Performing the sequential and random memory test
next.
The memory below 1 MB has been tested and initialized. Adjusting
the displayed memory size for relocation and shadowing next.
The memory size display was adjusted for relocation and shadow
ing.
Testing the memory above 1 MB next.
The memory above 1 MB has been tested and initialized. Saving
the memory size information next.
The memory size information and the CPU registers are saved.
Entering real mode next.
Shutdown was successful. The CPU is in real mode. Disabling the
Gate A20 line, parity, and the NMI next.
The A20 address line, parity, and the NMI are disabled. Adjusting
the memory size depending on relocation and shadowing next.
The memory size was adjusted for relocation and shadowing.
Clearing the Hit <DEL> message next.
The Hit <DEL> message is cleared. The <WAIT...> message is
displayed. Starting the DMA and interrupt controller test next.
Appendix B: BIOS POST Checkpoint Codes
B-5
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