Model A36R
Figure 9: BiSS timing diagram
Parameter
Permissible Clock Period
Permissible Clock Frequency
Processing Time with Start Bit Delay
Adaptive Timeout at DATA Line
* t
measured as first 1.5 x T(CLCK) for each frame.
init
Table 9: BiSS timing and performance characteristics
8.4 Cable Length vs. Frequency
The maximum clock frequency supplied by the master is limited by cable length.
Cable Length
< 150 m (492 ft)
> 150 m
Note: This assumes shielded twisted pair cable and proper termination are used. Lower clock frequency may be required at
extreme cable lengths.
Table 10: Cable length vs. max clock frequency (BiSS C)
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Symbol
t
C
1 / t
C
t
busy
t
out
Max Clock Frequency
10 MHz
5 MHz
PAGE 21 OF 33
T E C H N I C A L R E F E R E N C E M A N U A L
Description
100 ns min
10 MHz
5 x t
max
C
Min = 0.075 μs
Typ = t
+ 0.2 μs *
init
Max = 24 μs
EPC Technical Reference Manual – Model A36R
© 2023 Encoder Products Company, REV 11/08/2023
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