Ssi Communication Timing; Figure 7: Ssi Timing Diagram; Table 7: Ssi Timing And Performance Characteristics - Encoder A36R Technical Reference Manual

Model A36R
If only position data is needed, it is possible to send only the number of clock cycles
matching the position bit length (MT + ST bits) to disregard the nERR/nWARN and CRC
bits at the end of the packet.
An optional 6-bit life cycle counter is also available upon special request. Please contact EPC if this option is required.

7.3 SSI Communication Timing

Communication via SSI requires slave timeout (t
encoder will resend the same information and will not latch the updated position. Figure 7 and Table 7 below provide details on
timing requirements while using the Model A36R with SSI.

Figure 7: SSI timing diagram

Parameter
Permissible Frame Repetition
REQ Signal Low Level Duration
Permissible Clock Period
Clock Signal High Level Duration
Clock Signal Low Level Duration
Propagation Delay
Slave Timeout
*May increase with long cable lengths.

Table 7: SSI timing and performance characteristics

1-800-366-5412 | encoder.com | sales@encoder.com
) be met before additional clock signals may be sent. If t
out
Symbol Min
t Allow t to elapse
frame out
t 50 ns
RQ
t 200 ns
C
t 25 ns
L1
t 25 ns
L2
t --
p3
t 16 μs
out
PAGE 18 OF 33
T E C H N I C A L R E F E R E N C E M A N U A L
Typ Max
-- Indefinite
-- --
-- --
- t
out
-- t
out
-- 132 ns*
20 μs 24 μs
is not met, the
out
EPC Technical Reference Manual – Model A36R
© 2023 Encoder Products Company, REV 11/08/2023