Ssi Packet Structure; Figure 5: Typical Ssi Point-To-Point Connections; Figure 6: Ssi Data Exchange - Encoder A36R Technical Reference Manual

Model A36R
T E C H N I C A L R E F E R E N C E M A N U A L

Figure 5: Typical SSI point-to-point connections

The SSI master controls the data flow from the encoder data output by sending clock pulses to the encoder clock (CLK) inputs. The
encoder electronics respond to the first falling edge of the clock sequence by freezing the current position value and starting the
serial output of the data bits. On every following rising clock edge from the master, one data bit is transmitted by the encoder.
Additional details on timing and data structure can be found in the next section.

7.2 SSI Packet Structure

The data frame for the Model A36R with SSI protocol is shown in Figure 6 below.

Figure 6: SSI data exchange

The data frame consists of multi-turn position data (right-aligned), single-turn position data (left-aligned), low-active err bit nERR,
low-active warning bit nWARN, and a 6-bit CRC.
If the encoder was configured with no multi-turn bits, only single-turn position data will be sent.
nERR and nWARN can be monitored to provide indication of encoder errors and warnings respectively. See Section 6.2 for details.
Battery early warning and battery error will trigger these bits as well for encoders configured with the low power backup (XXL)
option.
The 6-bit CRC can be used to provide error checking to the critical encoder position data. Further details on CRC can be found in
Section 9. A 16-bit CRC is available upon special request. Please contact EPC if this option is required.
EPC Technical Reference Manual – Model A36R
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