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Functional Description
3
Mezzanine
SDRAM Memory
Size
32 Mbytes
64 Mbytes
128 Mbytes
256 Mbytes
512 Mbytes
768 Mbytes
3-10
The memory mezzanine will have one or two SPD SROMs installed,
depending on the number of memory banks installed; one for banks C and
D and one for banks E and F. Each SROM is a 3.3V, 256 x 8, Serial
EEPROM device (AT24C02) used for Serial Presence Detect (SPD)
memory configuration information.
The memory mezzanine has a MPC952 PLL clock driver implemented as
a zero delay buffer. This buffers the SDRAM clock from the PrPMC750
and creates 10 low skew clock outputs to drive the SDRAM devices on the
mezzanine.
The addition of the memory mezzanine and the number of banks on the
mezzanine may restrict the maximum operating frequency of the
PPC/memory bus. The address and control lines are buffered with flow-
thru buffers and the data lines are terminated with 10 ohm series resistors.
Adding the memory mezzanine connector, which is located on side 2 of the
PrPMC750, will extend the side 2 height above the standard 3.5 mm
envelope. Therefore, the mezzanine connector is a population option only
installed on versions of the PrPMC750 which are required to support
memory expansion. Refer to the following table for memory size options
per bank. Note that since there is only one SPD SROM for Banks C/D and
one for Banks E/F, the bank pairs must use the same memory device if both
banks are populated.
Table 3-3. Mezzanine SDRAM Memory Size Options
Device Size
64 Mbit
64 Mbit
64 Mbit
128 Mbit
256 Mbit
256 Mbit
Device
Number of
Organization
Devices
4Mx16
8Mx8
8Mx8
16Mx8
32Mx8
32Mx8
16Mx16
Computer Group Literature Center Web Site
Banks
Installed
5
E
9
C
18
C & D
18
C & D
18
C & D
18
C, D
10
E, F
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