Related Manuals for Texas Instruments TPS70351EVM
Summary of Contents for Texas Instruments TPS70351EVM
- Page 1 TPS70351EVM Low Dropout, Dual Output Linear Regulator EVM For Using the TPS70351 User’s Guide October 2000 POWER MANAGEMENT PRODUCTS SLVU036...
- Page 2 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability.
- Page 3 Preface About This Manual This user’s guide describes the TPS70351EVM low-dropout, dual-output evaluation module (SLVP165). The SLVP165 provides a convenient method for evaluating the performance of a dual-output linear regulator. How to Use This Manual Chapter 1 Introduction Chapter 2 EVM Adjustments and Test Points...
- Page 4 Related Documentation From Texas Instruments Related Documentation From Texas Instruments TPS70351 data sheets (literature number SLVS285) Trademarks PowerPAD is a trademark of Texas Instruments.
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Page 5: Table Of Contents
Running Title—Attribute Reference Contents Introduction ..............1–1 Low Dropout Voltage Linear Regulator Circuit Operation . - Page 6 Running Title—Attribute Reference Figures 1–1 Typical LDO Application ............1–2 SLVP165B EVM Universal LDO Tester Schematic Diagram .
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Page 7: Introduction
Chapter 1 Introduction This user’s guide describes the TPS70351EVM165 low-dropout, dual-output evaluation module (SLVP165B). LDOs provide ideal power supplies for rapidly transitioning DSP loads. The TPS703xx family of devices is designed to provide a complete power management solution for DSP, processor power, ASIC, FPGA, and digital applications where dual output voltage regulators are required. -
Page 8: Low Dropout Voltage Linear Regulator Circuit Operation
Low Dropout Voltage Linear Regulator Circuit Operation 1.1 Low Dropout Voltage Linear Regulator Circuit Operation In TI’s low dropout voltage linear regulator topology, a PMOS transistor is used for the pass element. Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low and is directly proportional to the output current. -
Page 9: Design Strategy
24 pin TSSOP with PowerPAD > 47 µF (ceramic) Minimum output capacitor Available voltage option [V] 3.3/1.5, 3.3/1.2, 3.3/1.8, 3.3/2.5, and adj/adj Dual output LDO, power-up sequencing, DSP application, Performance advantage PG and RESET PowerPAD is a trademark of Texas Instruments. Introduction... -
Page 10: Schematic
Schematic 1.3 Schematic Figure1–2 shows the SLVP165 EVM schematic diagram. Figure 1–2. SLVP165B EVM Universal LDO Tester Schematic Diagram Introduction... -
Page 11: Bill Of Materials
Bill of Materials 1.4 Bill of Materials Table 1–2 lists materials required for the SLVP165 EVM. Table 1–2. SLVP165B EVM Bill of Materials Ref Des Qty Part Number Description Size ECJ-2VF1C105Z Capacitor, ceramic, 1.0 uF, 16 V, Panasonic 80% – 20%, Y5V Capacitor, tantalum, 100 µF, 10 V, C2 –... - Page 12 Bill of Materials Table 1–2. SLVP165B EVM Bill of Materials (Continued) Ref Des Part Number Description Size Resistor, chip, 33 Ω, 1 W, 5% R15 – 19 ERJ–1WYJ33OU Panasonic 2512 R15A – 19A Resistor, chip, 10 Ω, 1 W, 5% R20 –...
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Page 13: Board Layout
Board Layout 1.5 Board Layout Figures 1–3 through 1-5 show the board layout for the SLVP165B EVM. Figure 1–3. Top Layer Top Layer Figure 1–4. Bottom Layer (top view) Bottom Layer Introduction... -
Page 14: Assembly Drawing (Top Assembly)
Board Layout Figure 1–5. Assembly Drawing (top assembly) Top Assembly Introduction... -
Page 15: Evm Adjustments And Test Points
Chapter 2 EVM Adjustments and Test Points This chapter explains the following EVM adjustment modes: Adjustment by switch and jumper Adjustment through changing components Figure 2–1 shows the locations of the adjustment points on the board. Topic Page Adjustment by Switch and Jumpers . -
Page 16: Adjustment By Switch And Jumpers
Adjustment by Switch and Jumpers 2.1 Adjustment by Switch and Jumpers S1 switches the transient generator on or off. Table 2–1 lists adjustments that can be made by jumpers. Table 2–1. Jumper Functions Jumper Setting Functional Description Short 1-2 – MR2 tied to GND RESET follows MR2 Short 2-3 –... -
Page 17: Adjustment Through Component Changes
Adjustment Through Component Changes 2.2 Adjustment Through Component Changes Through minor soldering work, the onboard device can be changed to any of the fixed-voltage members of the TPS703xx LDO family. In addition, Table 2–2 summarizes the most common components which a user might wish to re- place in order to more fully characterize the LDO. -
Page 18: Test Setup
Test Setup 5) Verify that the output voltage (measured at the V and V pins re- OUT1 OUT2 spectively) has the desired value. 6) Table 2–4 shows the three recommended options for loading each regula- tor. Table 2–4. Regulator Loading Options JP5–Regulator 1 Type JP6–Regulator 2... -
Page 19: Circuit Design
Chapter 3 Circuit Design This chapter describes the LDO circuit design procedure. Topic Page ESR and Transient Response ........3–2 Circuit Design... -
Page 20: Esr And Transient Response
ESR and Transient Response 3.1 ESR and Transient Response LDOs typically require an external output capacitor for stability. In fast transient response applications, capacitors are used to support the load current while the LDO amplifier is responding. In most applications, one capacitor is used to support both functions. - Page 21 ESR and Transient Response When C is conducting current to the load, initial voltage at the load will be = V(C ) – V . Due to the discharge of C , the output voltage V will drop continuously until the response time t of the LDO is reached and the LDO will resume supplying the load.
- Page 22 Circuit Design...
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Page 23: Test Results
Chapter 4 Test Results This chapter presents laboratory test results for the TPS70351 LDO design. Topic Page Test Results ..........4–2 Test Results... -
Page 24: Test Results
Test Results 4.1 Test Results Figures 4–1 through 4–10 show the results of various test conditions using the TPS70351 device. In Figure 4–1, the onboard transient generator is used to pulse I (CH1) OUT1 on V (CH2–AC) from 1 mA to 1 A. A current loop was added to the board OUT1 to measure the load current. -
Page 25: Timing When Sequence Is High
Test Results In Figure 4-3, ENABLE (CH1) is pulsed. When SEQ is high, V (CH2) OUT1 powers up after V (CH3) reaches 85% of its regulated output. PG1 (CH4), OUT2 which is tied to MR1, goes high when V reaches 95% of its regulated OUT1 voltage. -
Page 26: Timing Including Reset
Test Results In Figure 4–5, ENABLE (CH1) is pulsed. SEQUENCE can be either low or high. With PG1 tied to MR1, RESET (CH4) goes high 120 ms after both V OUT1 and V have reached 95% of their respective regulated output voltages. OUT2 Figure 4–5. - Page 27 Test Results In Figure 4–7, V (CH1) is pulsed into a shorted condition. Because OUT1 SEQUENCE is high, V (CH2) is not disabled after the internal current limit OUT2 circuitry disables V . PG1 (CH3), which is tied to MR1, goes low when OUT1 falls below 95% of its regulated voltage.
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Page 28: Timing When Mr Is Toggled
Test Results In Figure 4–9, V is pulsed into a shorted condition. Because SEQUENCE OUT2 is high, V is disabled after the internal current limit circuitry disables OUT1 . PG1 (CH3), which is tied to MR1, goes low when V falls below OUT2 OUT1... - Page 29 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Texas Instruments TPS70351EVM-165...
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