Texas Instruments TPS59640EVM-751 User Manual
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Texas Instruments TPS59640EVM-751 User Manual

Texas Instruments TPS59640EVM-751 User Manual

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The TPS59640EVM-751 evaluation module (EVM) is a complete solution for the Intel™ IMVP-7 Serial VID
(SVID) Power System from a 9-V to 20-V input bus. This EVM uses the TPS59640 for IMVP-7 3-Phase
CPU and 1-Phase GPU Vcore, TPS51219 for 1.05VCCIO, TPS51916 for DDR3L/DDR4 memory rail
(1.2VDDQ, 0.6VTT, and 0.6VTTREF). The TPS59640EVM-751 also uses the 5-mm x 6-mm TI power
block MOSFET (CSD87350Q5D) for high-power density and superior thermal performance.
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TPS59640EVM-751 Power System Block Diagram
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Intel is a trademark of Intel Corporation.
Windows is a trademark of Microsoft Corporation.
SLUU796 - January 2012
Submit Documentation Feedback
Using the TPS59640EVM-751 IMVP-7, 3-Phase
CPU/1-Phase GPU SVID Power System
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Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID
Copyright © 2012, Texas Instruments Incorporated
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List of Figures
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User's Guide
SLUU796 - January 2012
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Power System
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  • Page 1: Table Of Contents

    Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System The TPS59640EVM-751 evaluation module (EVM) is a complete solution for the Intel™ IMVP-7 Serial VID (SVID) Power System from a 9-V to 20-V input bus. This EVM uses the TPS59640 for IMVP-7 3-Phase CPU and 1-Phase GPU Vcore, TPS51219 for 1.05VCCIO, TPS51916 for DDR3L/DDR4 memory rail...
  • Page 2 CPU1 Switching Node ..................CPU1 Switching Node and Ripple ................CPU1 Dynamic VID: SetVID-Slow/Slow ................CPU1 Dynamic VID: SetVID-Fast/Fast SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...
  • Page 3 TPS59640EVM-751 Internal Layer 4 ................... TPS59640EVM-751 Internal Layer 5 ................... TPS59640EVM-751 Internal Layer 6 ................... TPS59640EVM-751 Internal Layer 7 SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 4: Contents 1 Description

    Bill of Materials Description The TPS59640EVM-751 evaluation module is designed to use a 9-V to 20-V input bus to produce six regulated outputs for the IMVP-7 SVID CPU/GPU Power System. The TPS59640EVM-751 is specially designed to demonstrate the TPS59640 full IMVP-7 mobile feature while providing a GUI communication program and a number of test points to evaluate the static and dynamic performance of the TPS59640.

  • Page 5: Tps59640Evm-751 Power System Block Diagram

    VCCIO: 0A-10A GUI communication TMS320F2806PZS USB Cable TUSB3410RHB Host Computer Figure 1. TPS59640EVM-751 Power System Block Diagram SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 6: Electrical Performance Specifications

    Selectable per phase Switching frequency Selectable Full load efficiency VBAT=12 V, 1.05 V/94 A at 300 kHz 80.05% Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID SLUU796 – January 2012 Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...
  • Page 7 Output over current Switching frequency Selectable Full-load efficiency VBAT = 12 V, 1.2 V/15 A 90.62% Operating temperature °C SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 8: Schematic

    Note: Jumpers set to default locations; see Section 6 of this user’s guide. Schematic Figure 3. TPS59640EVM-751 Schematic (1 of 13) SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 9: Tps59640Evm-751 Schematic (2 Of 13)

    Schematic www.ti.com Figure 4. TPS59640EVM-751 Schematic (2 of 13) SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 10: Tps59640Evm-751 Schematic (3 Of 13)

    Schematic www.ti.com Figure 5. TPS59640EVM-751 Schematic (3 of 13) SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 11: Tps59640Evm-751 Schematic (4 Of 13)

    Schematic www.ti.com Figure 6. TPS59640EVM-751 Schematic (4 of 13) SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 12: Tps59640Evm-751 Schematic (5 Of 13)

    Schematic www.ti.com Figure 7. TPS59640EVM-751 Schematic (5 of 13) SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 13: Tps59640Evm-751 Schematic (6 Of 13)

    Schematic www.ti.com Figure 8. TPS59640EVM-751 Schematic (6 of 13) SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 14: Tps59640Evm-751 Schematic (7 Of 13)

    Schematic www.ti.com Figure 9. TPS59640EVM-751 Schematic (7 of 13) SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 15: Tps59640Evm-751 Schematic (8 Of 13)

    Schematic www.ti.com Figure 10. TPS59640EVM-751 Schematic (8 of 13) SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 16: Tps59640Evm-751 Schematic (9 Of 13)

    Schematic www.ti.com Figure 11. TPS59640EVM-751 Schematic (9 of 13) SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 17: Tps59640Evm-751 Schematic (10 Of 13)

    Schematic www.ti.com Figure 12. TPS59640EVM-751 Schematic (10 of 13) SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 18: Tps59640Evm-751 Schematic (11 Of 13)

    Schematic www.ti.com Figure 13. TPS59640EVM-751 Schematic (11 of 13) SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 19: Tps59640Evm-751 Schematic (12 Of 13)

    Schematic www.ti.com Figure 14. TPS59640EVM-751 Schematic (12 of 13) SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 20: Tps59640Evm-751 Schematic (13 Of 13)

    Schematic www.ti.com Figure 15. TPS59640EVM-751 Schematic (13 of 13) SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 21: Test Setup

    4. Double-click on this setup.exe. This loads the TUSB drivers files to the host computer on C:\Program Files\Texas Instruments Inc\TUSB3410 Single Driver installer\DISK1 5. Then, go to this location on the host computer (C:\Program Files\Texas Instruments Inc\TUSB3410 Single Driver installer\DISK1), and double-click setup.exe. This installs the TUSB driver.

  • Page 22: Recommended Wire Gage

    (2-foot output, 2-foot return) Recommended Test Setup Figure 17 is the recommended test setup to evaluate the TPS59640EVM-751. Working at an ESD workstation, ensure that any wrist straps, bootstraps, or mats are connected referencing the user to earth ground before handling the EVM.

  • Page 23: Usb Cable Connections

    4. Connect a current meter A1 between 12VBAT DC source and J30 to measure the 12VBAT input current. SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 24: Output Connections

    Sixth (11-12 pin shorted) 30.1k Level 3 Seventh (13-14 pin shorted) 24.3k Level 2 Right (15-16 pin shorted) 20.0k SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 25: Cpu Frequency Selection

    Sixth (11-12 pin shorted) 30.1k Level 3 Seventh (13-14 pin shorted) 24.3k Level 2 Right(15-16 pin shorted) 20.0k SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 26: Gpu Overshoot/Undershoot Reduction Selection

    Push S2 (lower) to ON position Enable 10-A onboard dynamic load at VCCIO Push S2 (lower) to OFF position Disable 10-A onboard dynamic load at VCCIO Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID SLUU796 – January 2012 Power System Submit Documentation Feedback...

  • Page 27: Vddq, 0.6V Vtt And 0.6V Vttref Configuration

    Jumper shorts on pin 1 and pin 2 VCCIO: 1.05 V Jumper shorts on pin 2 and pin 3 VCCIO: 1.00 V SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 28: Test Procedure

    18. Decrease LOAD to 0 A, and disconnect the LOAD from terminal J1, J5, and J6. 19. Disconnect V3 from J14. 20. Disconnect scope probe from TP27. SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 29: Tps59640Evm-751 Cpu Gui Setup Window

    11. Disconnect V3 from J16. 12. Disconnect scope probe from TP37. 13. Exit SVID GUI window: click File → click Exit. SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 30: Tps59640Evm-751 Gpu Gui Setup Window

    1. Connect the LOAD to VCCIO terminal J24 and V3 at J25. Ensure correct polarity. 2. Push S1 to ON position to enable the VCCIO controller. VCCIO EN and PGOOD LEDs light up. SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback...

  • Page 31: Equipment Shutdown

    1. Shut down load. 2. Shut down 12VBAT and 5Vin. 3. Shut down oscilloscope. 4. Shut down host computer. SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 32: Performance Data And Typical Characteristic Curves

    Performance Data and Typical Characteristic Curves www.ti.com Performance Data and Typical Characteristic Curves Figure 20 through Figure 91 present typical performance curves for TPS59640EVM-751. Jumpers are set to default locations; see Section 6 of this user’s guide CPU3-Phase Operation V = 9 V...

  • Page 33: Cpu3 Switching Node (Ripple)

    CH3: Vcore CH3: Vcore CH4: VDIO CH4: VDIO Figure 26. CPU3 Dynamic VID:SetVID-Fast/Fast Figure 27. CPU3 Dynamic VID:SetVID-Decay/Fast SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 34: Cpu3 Output Load Insertion With Osr/Usr20K (Min)

    Figure 29. CPU3 Output Load Release With OSR/USR OSR/USR20k (Min) 20k (Min) Figure 30. CPU3 Bode Plot at 12Vin, 1.05 V/60 A SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 35: Cpu3 Mosfet

    Figure 31. CPU3 MOSFET Figure 32. CPU3 IC Test condition: CPU3 12Vin, 1.05 V/60 A, no airflow SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 36: Cpu 2-Phase Operation

    CH3: Vcore CH3: Vcore CH4: CPGOOD CH4: CPGOOD Figure 35. CPU2 Enable Turnon Figure 36. CPU2 Enable Turnoff SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 37: Cpu2 Switching Node (Ripple)

    CH3: Vcore CH4: VDIO CH4: VDIO Figure 39. CPU2 Dynamic VID: SetVID-Fast/Fast Figure 40. CPU2 Dynamic VID: SetVID-Decay/Fast SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 38: Cpu2 Bode Plot At 12Vin, 1.05 V/55 A

    Figure 41. CPU2 Output Load Insertion With OSR/USR Figure 42. CPU2 Output Load Release With OSR/USR 20k (Min) 20k (Min) Figure 43. CPU2 Bode Plot at 12Vin, 1.05 V/55 A SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 39: Cpu2 Mosfet

    Figure 44. CPU2 MOSFET Figure 45. CPU2 IC Test condition: CPU2 12Vin, 1.05 V/55 A, no airflow SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 40: Cpu 1-Phase Operation

    CH3: Vcore CH3: Vcore CH4: CPGOOD CH4: CPGOOD Figure 48. CPU1 Enable Turnon Figure 49. CPU1 Enable Turnoff SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 41: Cpu1 Switching Node

    CH3: Vcore CH4: CPGOOD CH4: CPGOOD Figure 52. CPU1 Dynamic VID: SetVID-Slow/Slow Figure 53. CPU1 Dynamic VID: SetVID-Fast/Fast SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 42: Cpu1 Dynamic Vid: Setvid-Decay/Fast

    OSR/USR = 20 k - Min CH1: DYN_C CH2: CSW1 CH4: Vcore Figure 56. CPU1 Output Load Release With OSR/USR 20k (Min) SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 43: Cpu1 Bode Plot At 12Vin, 1.05 V/33 A

    Figure 58. CPU1 MOSFET Figure 59. CPU1 IC Test condition: CPU1 12Vin, 1.05 V/33 A, no airflow SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 44: Gpu Operation

    CH3: G_Vcore CH3: G_Vcore CH4: GPGOOD CH4: GPGOOD Figure 62. GPU Enable Turnon Figure 63. GPU Enable Turnoff SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 45: Gpu Switching Node

    CH3: G_Vcore CH4: GPGOOD CH4: GPGOOD Figure 66. GPU Dynamic VID: SetVID-Slow/Slow Figure 67. GPU Dynamic VID: SetVID-Fast/Fast SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 46: Gpu Dynamic Vid: Setvid-Decay/Fast

    OSR/USR = 20 k - Min CH1: DYN_G CH2: GSW CH4: G_Vcore Figure 70. GPU Output Load Release With OSR/USR 20k (Min) SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 47: Gpu Bode Plot At 12Vin, 1.23 V/33 A

    Figure 72. GPU MOSFET Figure 73. GPU IC Test condition: GPU 12Vin, 1.23 V/33 A, no airflow SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 48: Vccio

    CH2: VCCIO CH2: VCCIO CH3: VCCIO_PG CH3: VCCIO_PG Figure 76. 1.05-V Enable Turnon Figure 77. 1.05-V Enable Turnoff SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 49: V Switching Node

    CH4: VCCIO Output Current Figure 80. 1.05-V Transient DCM to CCM Figure 81. 1.05-V Transient CCM to DCM SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 50: Tps51219 Thermal

    Performance Data and Typical Characteristic Curves www.ti.com Figure 82. TPS51219 Thermal Test condition: 12Vin, 1.05 V/15 A, no airflow SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 51: Vddq

    CH3: VDDQ CH3: VDDQ CH4: VDDQ_PG CH4: VDDQ_PG Figure 85. 1.2-V Enable Turnon Figure 86. 1.2-V Enable Turnoff SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 52: V Switching Node

    CH4: VDDQ Output Current Figure 89. 1.2-V Transient DCM to CCM Figure 90. 1.2-V Transient CCM to DCM SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 53: Evm Assembly Drawings And Pcb Layout

    The EVM has been designed using an eight-layer circuit board with 2 oz o0f copper on outside layers. EXAS NSTRUMENTS Figure 92. TPS59640EVM-751 Top Layer Assembly Drawing (Top View) SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright ©...

  • Page 54: Tps59640Evm-751 Bottom Assembly Drawing (Bottom View)

    EVM Assembly Drawings and PCB layout www.ti.com Figure 93. TPS59640EVM-751 Bottom Assembly Drawing (Bottom View) Figure 94. TPS59640EVM-751 Top Copper SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 55: Tps59640Evm-751 Bottom Copper

    EVM Assembly Drawings and PCB layout www.ti.com Figure 95. TPS59640EVM-751 Bottom Copper Figure 96. TPS59640EVM-751 Internal Layer 2 SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 56: Tps59640Evm-751 Internal Layer

    EVM Assembly Drawings and PCB layout www.ti.com Figure 97. TPS59640EVM-751 Internal Layer 3 Figure 98. TPS59640EVM-751 Internal Layer 4 SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 57: Tps59640Evm-751 Internal Layer

    EVM Assembly Drawings and PCB layout www.ti.com Figure 99. TPS59640EVM-751 Internal Layer 5 Figure 100. TPS59640EVM-751 Internal Layer 6 SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 58: Tps59640Evm-751 Internal Layer

    EVM Assembly Drawings and PCB layout www.ti.com Figure 101. TPS59640EVM-751 Internal Layer 7 SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 59: Bill Of Materials

    Resistor, Chip, 71.5k, 1/10W, 1%, 0603 R119, R120, R136, R203, Resistor, Chip, 180, 1/10W, 1%, 0603 R204, R205, R209 SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...
  • Page 60 Resistor, Chip, 42.2k, 1/10W, 1%, 0603 R74, R75, R76, R98, R99, Resistor, Chip, 100k, 1/10W, 1%, 0603 R100, R152, R173 SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...
  • Page 61 UCC27324D Crystal, controlled oscillators, 0.150”x0.528” ABRACON ABLS-20.000MHZ-B2-T Crystal, controlled oscillators, 0.150”x0.528” ABRACON ABLS-12.000MHZ-B2-T Socket, CPU Molex rPGA989 SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...
  • Page 62 Evaluation Board/Kit Important Notice Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must have electronics training and observe good engineering practice standards.
  • Page 63 Evaluation Board/Kit Important Notice Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must have electronics training and observe good engineering practice standards.
  • Page 64 Any exceptions to this are strictly prohibited and unauthorized by Texas Instruments unless user has obtained appropriate experimental/development licenses from local regulatory authorities, which is responsibility of user including its acceptable authorization.
  • Page 65 FCC Interference Statement for Class B EVM devices This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications.
  • Page 66 Also, please do not transfer this product, unless you give the same notice above to the transferee. Please note that if you could not follow the instructions above, you will be subject to penalties of Radio Law of Japan. Texas Instruments Japan Limited (address) 24-1, Nishi-Shinjuku 6 chome, Shinjuku-ku, Tokyo, Japan http://www.tij.co.jp...
  • Page 67 FDA Class III or similar classification, then you must specifically notify TI of such intent and enter into a separate Assurance and Indemnity Agreement. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2012, Texas Instruments Incorporated...
  • Page 68 TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2021, Texas Instruments Incorporated...

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