Texas Instruments TPS51100 User Manual
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Texas Instruments TPS51100 User Manual

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Using the TPS51100
User's Guide
Literature Number: SLUU201
JULY 2004

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Summary of Contents for Texas Instruments TPS51100

  • Page 1 Using the TPS51100 User's Guide Literature Number: SLUU201 JULY 2004...
  • Page 2 S3 and S5 sleep states. Description The TPS51100 is designed to provide proper termination voltage for DDR memory modules covering both the DDRI (2.5 V/1.25 V) and DDR2 (1.8 V/0.9 V) specifications with minimal external components. The high-speed LDO allows designs with fewer and smaller external capacitors, reducing the size and cost of the dual data rate memory power solution.

  • Page 3: Electrical Performance Specifications

    ½ this VDDQSNS voltage. This allows the user to evaluate the TPS51100 under a variety of conditions. The TPS51100EVM should not be operated when this jumper is not in place and the EVM should be powered down prior to changing the jumper position.
  • Page 4 VTT and VTTREF termination and buffered reference voltages. This allows the user to evaluate the TPS51100 under a variety of conditions or adjust the output voltage with an external system. Even in this configuration, VDDQ must be connected to provide the LDOIN source voltage and current. To configure the TPS51100EVM for external reference voltage, set the JP1 jumper in the right horizontal position.
  • Page 5 V5IN V5IN TPS51100 operating current and powers the S3 and S5 sleep state switches. Core Voltage Source (V VDDQ IN is a DC voltage source capable of delivering 1.5 VDC to 3.4 VDC at 3.5 ADC with a power VDDQ IN handling capability of at least 12 W.
  • Page 6 EVM Assembly Drawing and Layout TPS51100 is built on a double sided copper clad FR4 PCB 3.0”× 3.0” and 0.062 thick. Figure 4 through Figure 7 detail the PCB assembly, silk screen and copper layers for TPS51100EVM. These figures are provided for reference and evaluation purposes only.
  • Page 7 EVM Assembly Drawing and Layout Figure 4. Top Side Component Output (Top View) Figure 6. Top Copper Layer (Top View) Figure 5. Top Silk Screen (Top View) Figure 7. Bottom Copper Layer (Bottom View) SLUU201 – JULY 2004 Using the TPS51100...
  • Page 8 IC, High Performance DDRI&II 3A LDO & Buffered HTTSOP-10 TPS51100DGQ Reference PCB, 2-layer FR4, 3.0" x 3.0" 0.063thk 2.25 × 3.20 HPA078A Shunt, 100 mil jumper 0.1 × 0.2 Sullins PJ-19-2-0 Bumpon, Transparent 0.44 × 0.2 SJ5303 Using the TPS51100 SLUU201 – JULY 2004...

  • Page 9: Fcc Warnings

    EVM IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not considered by TI to be fit for commercial use.

  • Page 10: Important Notice

    TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products...

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