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The clock input is supplied by way of a single-ended signal to an SMA connector and transformer coupled
producing a differential clock signal for the ADS58H40.
Power to the EVM is typically supplied by a single 6-V power brick. Banana jacks may also be used to
supply power to the EVM. All necessary voltages for the ADS58H40 are derived from the 6-V input
connection.
1.2
EVM Power Supply
Figure 2
illustrates the power supply options available on the EVM. Jumpers are used to choose the
power supply options, with the default jumper positions indicated by the darker portion of the jumper that
represents the presence of the jumper. For jumper and feedback resistor configuration, see
J1
J2
Protection Circuit
6 V
PWR IN
J3
GND
Power Supply
JP2
Options
Option #1
1-2
(Default)
Option #2
2-3
The default power path has an efficient dual output DC-DC switching power supply to first step down the
input supplies for the low-noise LDOs. The low-noise LDOs generate the 3.3 V and 1.9 V for the ADC
power.
The low-noise LDOs can be bypassed, allowing the DC/DC power supply to directly power the ADC. In
this implementation, adjust the feedback resistors of the DC/DC converter accordingly.
SLAU455 – August 2012
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TPS2400
Overvoltage
TPS62420
Dual Output
DC/DC Converter
Figure 2. Simplified ADS58H40 EVM Power Supply
Table 1. Power Supply Options
JP3
JP4
JP5
R3
649
1-2
1-2
1-2
kΩ
536
2-3
2-3
2-3
kΩ
Copyright © 2012, Texas Instruments Incorporated
JP2
1
TPS7A8001
LDO 3.3 V
Low Noise LDO
JP6
1
TPS7A8001
LDO 1.9 V
Low Noise LDO
R7
Dual outputs DC/DC converter supplies 3.85 V and 2.4 V to two
536
low-noise LDOs. The low-noise LDOs output 3.3 V and 1.9 V,
kΩ
respectively.
390
Low-noise LDOs are bypassed. DC/DC converter powers the
kΩ
ADC directly.
Introduction
Table
1.
JP3
1
To ADC
JP5
1
To ADC
Comment
ADS58H40 EVM
3
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