Page 1: Features
USB 1.1 and 2.0 Full Speed Compliant Module with Interrupt on Transfer Completion – Endpoint 0 for Control Transfers: 32-byte FIFO – 6 Programmable Endpoints with In or Out Directions and with Bulk, Interrupt or AT89C5131A-L Isochronous Transfers • Endpoint 1, 2, 3: 32-byte FIFO •...
Page 2: Description
(T0/T1), a full duplex enhanced UART (EUART) and an on-chip oscillator. In addition, AT89C5131A-L has an on-chip expanded RAM of 1024 bytes (ERAM), a dual- data pointer, a 16-bit up/down Timer (T2), a Programmable Counter Array (PCA), up to 4 programmable LED current sources, a programmable hardware watchdog and a power-on reset.
Page 3: Block Diagram
AT89C5131A-L Block Diagram (1) (1) (1) (1) (1) (1) XTAL1 ERAM XTAL2 EEPROM EUART 32Kx8 Flash 1Kx8 4Kx8 Timer2 256x8 CORE PSEN Parallel I/O Ports & Ext. Bus Watch Timer 0 Regu- Ctrl Board Timer 1 lator VREF Port 0Port 1 Port 2 Port 3...
Page 4: Pinout Description
Pinout Description Pinout Figure 1. AT89C5131A-L 52-pin PLCC Pinout 5 4 3 2 1 52 51 50 49 48 P4.1/SDA P2.3/A11 P0.1/AD1 P2.4/A12 P0.2/AD2 P2.5/A13 P0.3/AD3 XTAL2 XTAL1 PLCC52 P2.6/A14 P0.4/AD4 P2.7/A15 P3.7/RD/LED3 P0.5/AD5 AVDD P0.6/AD6 P0.7/AD7 AVSS P3.6/WR/LED2 P3.0/RxD...
Page 5 AT89C5131A-L Figure 2. AT89C5131A-L 64-pin VQFP Pinout 62 61 60 59 58 57 56 55 54 53 51 50 49 P2.3/A11 P2.4/A12 P0.1/AD1 P2.5/A13 P0.2/AD2 XTAL2 XTAL1 P0.3/AD3 P2.6/A14 P2.7/A15 VQFP64 P0.4/AD4 AVDD P3.7/RD/LED3 P0.5/AD5 AVSS P0.6/AD6 P0.7/AD7 P3.0/RxD P3.6/WR/LED2...
Page 6: Signals
Signals All the AT89C5131A-L signals are detailed by functionality on Table 1 through Table 12. Table 1. Keypad Interface Signal Description Signal Alternate Name Type Description Function Keypad Input Lines KIN[7:0) Holding one of these pins high or low for 24 oscillator periods triggers a P1[7:0] keypad interrupt if enabled.
Page 7 AT89C5131A-L Table 4. Timer 0, Timer 1 and Timer 2 Signal Description (Continued) Signal Alternate Name Type Description Function Timer Counter 0 External Clock Input When Timer 0 operates as a counter, a falling edge on the T0 pin P3.4 increments the count.
Page 8 To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, leave XTAL2 unconnected. PLL Low Pass Filter input PLLF Receives the RC network of the PLL low pass filter (See Figure 4 on page 11 ). AT89C5131A-L 4338F–USB–08/07...
Page 9 AT89C5131A-L Table 10. USB Signal Description Signal Alternate Name Type Description Function USB Data + signal Set to high level under reset. USB Data - signal Set to low level under reset. USB Reference Voltage VREF Connect this pin to D+ using a 1.5 kΩ resistor to use the Detach function.
Page 10 Low Power versions. USB pull-up Controlled Output VREF is used to control the USB D+ 1.5 kΩ pull up. VREF The Vref output is in high impedance when the bit DETACH is set in the USBCON register. AT89C5131A-L 4338F–USB–08/07...
Page 11: Typical Application
AT89C5131A-L Typical Application Recommended External components All the external components described in the figure below must be implemented as close as possible from the microcontroller package. The following figure represents the typical wiring schematic. Figure 4. Typical Application 100nF 100nF 4.7µF...
Page 12: Pcb Recommandations
VRef USB Connector If possible, isolate D+ and D- signals from other signals with ground wires Figure 6. USB PLL AVss PLLF Components must be close to the microcontroller Isolate filter components with a ground wire AT89C5131A-L 4338F–USB–08/07...
Page 13: Clock Controller
Phase Lock Loop (PLL). All the internal clocks to the peripherals and CPU core are gen- erated by this controller. The AT89C5131A-L X1 and X2 pins are the input and the output of a single-stage on- chip inverter (see Figure 7) that can be configured with off-chip components as a Pierce oscillator (see Figure 8).
Page 14: Pll
Figure 8. Crystal Connection PLL Description The AT89C5131A-L PLL is used to generate internal high frequency clock (the USB Clock) synchronized with an external low-frequency (the Peripheral Clock). The PLL clock is used to generate the USB interface clock. Figure 9 shows the internal structure of the PLL.
Page 15 AT89C5131A-L PLL Programming The PLL is programmed using the flow shown in Figure 11. As soon as clock generation is enabled user must wait until the lock indicator is set to ensure the clock output is stable. Figure 11. PLL Programming Flow...
Page 16: Registers
System Clock Control bit Clear to select 12 clock periods per machine cycle (STD mode, F PER = Set to select 6 clock periods per machine cycle (X2 mode, F CPU = PER = Reset Value = 0000 0000b AT89C5131A-L 4338F–USB–08/07...
Page 17 AT89C5131A-L Table 15. CKCON1 (S:AFh) Clock Control Register 1 SPIX2 Bit Number Mnemonic Description Reserved The value read from this bit is always 0. Do not set this bit. SPI Clock This control bit is validated when the CPU clock X2 is set. When X2 is low, SPIX2 this bit has no effect.
Page 18: Sfr Mapping
SFR Mapping The Special Function Registers (SFRs) of the AT89C5131A-L fall into the following categories: • C51 core registers: ACC, B, DPH, DPL, PSW, SP • I/O port registers: P0, P1, P2, P3, P4 • Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H •...
Page 19 AT89C5131A-L The table below shows all SFRs with their address and their reset value. Table 18. SFR Descriptions Addressable Non-Bit Addressable CCAP0H CCAP1H CCAP2H CCAP3H CCAP4H UEPINT 0000 0000 0000 0000 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX...
Page 20 Word Stack Pointer LSB of SPX Data Pointer Low byte LSB of DPTR Data Pointer High byte MSB of DPTR Table 20. I/O Port SFRs Mnemonic Name Port 0 Port 1 Port 2 Port 3 Port 4 (2bits) AT89C5131A-L 4338F–USB–08/07...
Page 21 AT89C5131A-L Table 21. Timer SFR’s Mnemonic Name Timer/Counter 0 High byte Timer/Counter 0 Low byte Timer/Counter 1 High byte Timer/Counter 1 Low byte Timer/Counter 2 High byte Timer/Counter 2 Low byte Timer/Counter 0 and 1 TCON control Timer/Counter 0 and 1...
Page 22 PX1H PT0H PX0H IPL1 Interrupt Priority Control Low 1 PUSBL PSPIL PTWIL PKBL IPH1 Interrupt Priority Control High 1 PUSBH PSPIH PTWIH PKBH Table 26. PLL SFRs Mnemonic Name PLLCON PLL Control EXT48 PLLEN PLOCK PLLDIV PLL Divider AT89C5131A-L 4338F–USB–08/07...
Page 23 AT89C5131A-L Table 27. Keyboard SFRs Mnemonic Name Keyboard Flag KBF7 KBF6 KBF5 KBF4 KBF3 KBF2 KBF1 KBF0 Register Keyboard Input Enable KBE7 KBE6 KBE5 KBE4 KBE3 KBE2 KBE1 KBE0 Register Keyboard Level KBLS KBLS7 KBLS6 KBLS5 KBLS4 KBLS3 KBLS2 KBLS1...
Page 24 Clock Control 0 TWIX2 WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 CKCON1 Clock Control 1 SPIX2 LEDCON LED Control LED3 LED2 LED1 LED0 FCON Flash Control FPL3 FPL2 FPL1 FPL0 FMOD1 FMOD0 FBUSY EECON EEPROM Contol EEPL3 EEPL2 EEPL1 EEPL0 EEBUSY AT89C5131A-L 4338F–USB–08/07...
Page 25: Dual Data Pointer Register
AT89C5131A-L Dual Data Pointer The additional data pointer can be used to speed up code execution and reduce code size. Register The dual DPTR structure is a way by which the chip will specify the address of an exter- nal data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1.0 (see Table 32) that allows the program...
Page 26 DPS is toggled in the proper sequence matters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1' on entry. Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in the opposite state. AT89C5131A-L 4338F–USB–08/07...
Page 27: Program/Code Memory
AT89C5131A-L Program/Code The AT89C5131A-L implement 32 Kbytes of on-chip program/code memory. Figure 13 shows the split of internal and external program/code memory spaces depending on the Memory product. The Flash memory increases EPROM and ROM functionality by in-circuit electrical era- sure and programming.
Page 28: Flash Memory Architecture
This signal is active low during external code fetch or external code read (MOVC instruction). External Bus Cycles This section describes the bus cycles the AT89C5131A-L executes to fetch code (see Figure 15) in the external program/code memory. External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator clock periods in standard mode or 6 oscillator clock periods in X2 mode.
Page 29: Overview Of Fm0 Operations
AT89C5131A-L Figure 16. Flash Memory Architecture FFFFh 3 Kbytes Flash Memory Hardware Security (1 Byte) Boot Space Extra Row (128 Bytes) F400h Column Latches (128 Bytes) 7FFFh FM1 mapped between FFFFh and F400h when bit ENBOOT is set in 32 Kbytes...
Page 30 The bit FBUSY in FCON register is used to indicate the status of programming. FBUSY is set when programming is in progress. Selecting FM0/FM1 The bit ENBOOT in AUXR1 register is used to choose between FM0 and FM1 mapped up to F800h. AT89C5131A-L 4338F–USB–08/07...
Page 31 AT89C5131A-L Loading the Column Latches Any number of data from 1 byte to 128 bytes can be loaded in the column latches. This provides the capability to program the whole memory by byte, by page or by any number of bytes in a page.
Page 32 Figure 18. Flash and Extra Row Programming Procedure Flash Spaces Programming Column Latches Loading see Figure 17 Disable IT EA = 0 Launch Programming FCON = 5xh FCON = Axh FBusy Cleared? Erase Mode FCON = 00h End Programming Enable IT EA = 1 AT89C5131A-L 4338F–USB–08/07...
Page 33 AT89C5131A-L Hardware Security The following procedure is used to program the Hardware Security space and is sum- marized in Figure 19: • Set FPS and map Hardware byte (FCON = 0x0C) • Disable the interrupts. • Load DPTR at address 0000h.
Page 34 Read the byte in Accumulator by executing MOVC A, @A+DPTR with A = 0 & DPTR = 0000h. Figure 20. Reading Procedure Flash Spaces Reading Flash Spaces Mapping FCON = 00000xx0b Data Read DPTR = Address ACC = 0 Exec: MOVC A, @A+DPTR Erase Mode FCON = 00h AT89C5131A-L 4338F–USB–08/07...
Page 35: Registers
AT89C5131A-L Registers Table 36. FCON (S:D1h) Flash Control Register FPL3 FPL2 FPL1 FPL0 FMOD1 FMOD0 FBUSY Bit Number Mnemonic Description Programming Launch Command Bits FPL3:0 Write 5Xh followed by AXh to launch the programming according to FMOD1:0. (see Table 35.) Flash Map Program Space Set to map the column latch space in the data memory space.
Page 36: Flash Eeprom Memory
2. The Flash may be programmed or erased in the end-user application by calling low-level routines through a common entry point in the Boot Flash. 3. The Flash may be programmed using the parallel method . The bootloader and the Application Programming Interface (API) routines are located in the Flash Bootloader. AT89C5131A-L 4338F–USB–08/07...
Page 37: Flash Registers And Memory Map
API or with the parallel programming modes. This page, called “Extra Flash Memory”, is not in the internal Flash program memory addressing space. Hardware Registers The only hardware register of the AT89C5131A-L is called Hardware Security Byte (HSB). Table 37. Hardware Security Byte (HSB) BLJB...
Page 38 Software Registers Several registers are used, in factory and by parallel programmers, to make copies of hardware registers contents. These values are used by Atmel ISP (see Section “In-Sys- tem Programming (ISP)”). These registers are in the “Extra Flash Memory” part of the Flash memory. This block is also called ”XAF”...
Page 39 Copy of the Device ID #1: C51 X2, Electrically – Family Code Erasable Copy of the Device ID #2: – AT89C5131A-L 32 Kbyte Memories Copy of the Device ID #3: AT89C5131A-L 32 Kbyte, – Name revision 0 After programming the part by ISP, the BSB must be cleared (00h) in order to allow the application to boot at 0000h.
Page 40: Flash Memory Status
3. WARNING: Security level 2 and 3 should only be programmed after Flash and code verification. Flash Memory Status AT89C5131A-L parts are delivered with the ISP boot in the Flash memory. After ISP or parallel programming, the possible contents of the Flash memory are summarized in Figure 21: Figure 21.
Page 41: Eeprom Data Memory
AT89C5131A-L EEPROM Data Memory Description The 1-Kbyte on-chip EEPROM memory block is located at addresses 0000h to 03FFh of the ERAM memory space and is selected by setting control bits in the EECON register. A read in the EEPROM memory is done with a MOVX instruction.
Page 42: Registers
Clear to map the ERAM space during MOVX. Programming Busy flag Set by hardware when programming is in progress. EEBUSY Cleared by hardware when programming is done. Cannot be set or cleared by software. Reset Value = XXXX XX00b Not bit addressable AT89C5131A-L 4338F–USB–08/07...
Page 43: In-System Programming (Isp)
Erasure • The Atmel bootloader located in FM1 is activated by the application. Low level API routines (located in FM1)will be used to program FM0. The interface used for serial downloading to FM0 is the USB. API can be called also by user’s bootloader located in FM0 at [SBV]00h.
Page 44: Boot Process
- This bit indicates if on RESET the user wants to jump to this application at address @0000h on FM0 or execute the boot loader at address @F400h on FM1. - BLJB = 0 (i.e. bootloader FM1 executed after a reset) is the default Atmel factory pro- gramming.
Page 45: Application-Programming-Interface
Flash pages. All calls are made Programming-Interface by functions. All these APIs are described in detail in the following document on the Atmel web site. – Datasheet Bootloader USB AT89C5131. XROW Bytes The EXTRA ROW (XROW) includes 128 bytes.
Page 46 (because the HW conditions are never evaluated, as described in the USB Bootloader Datasheet). To go back to ISP, BLJB needs to be changed by a parallel programmer(or by the APIs). See a detailed description in the applicable Document. – Datasheet Bootloader USB AT89C5131. AT89C5131A-L 4338F–USB–08/07...
Page 47: On-Chip Expanded Ram (Eram)
Start AT89C5131A-L 1024 3FFh The AT89C5131A-L has on-chip data memory which is mapped into the following four separate segments. 1. The Lower 128 bytes of RAM (addresses 00h to 7Fh) are directly and indirectly addressable. 2. The Upper 128 bytes of RAM (addresses 80h to FFh) are indirectly addressable only.
Page 48 RAM) internal data memory. The stack may not be located in the ERAM. The M0 bit allows to stretch the ERAM timings; if M0 is set, the read and write pulses are extended from 6 to 30 clock periods. This is useful to access external slow peripherals. AT89C5131A-L 4338F–USB–08/07...
Page 49 AT89C5131A-L Table 45. AUXR Register AUXR - Auxiliary Register (8Eh) XRS1 XRS0 EXTRAM Number Mnemonic Description Disable Weak Pull Up Cleared to enabled weak pull up on standard Ports. Set to disable weak pull up on standard Ports. Reserved The value read from this bit is indeterminate. Do not set this bit...
Page 50: Timer 2
Timer 2 The Timer 2 in the AT89C5131A-L is the standard C52 Timer 2. It is a 16-bit timer/counter: the count is maintained by two cascaded eight-bit timer registers, TH2 and TL2. It is controlled by T2CON (Table 46) and T2MOD (Table 47) registers. Timer 2 operation is similar to Timer 0 and Timer 1.
Page 51: Programmable Clock Output
AT89C5131A-L Figure 26. Auto-reload Mode Up/Down Counter (DCEN = 1) CLK PERIPH C/T2 T2CON T2CON (DOWN COUNTING RELOAD VALUE) T2EX: if DCEN = 1, 1 = UP (8-bit) (8-bit) if DCEN = 1, 0 = DOWN if DCEN = 0, up counting...
Page 52 RCAP2H and RCAP2L registers. Figure 27. Clock-out Mode C/T2 = 0 CLK PERIPH T2CON (8-bit) (8-bit) OVERFLOW RCAP2L RCAP2H (8-bit) (8-bit) Toggle T2OE T2MOD Timer 2 T2EX EXF2 INTERRUPT T2CON EXEN2 T2CON AT89C5131A-L 4338F–USB–08/07...
Page 53 AT89C5131A-L Table 46. T2CON Register T2CON - Timer 2 Control Register (C8h) EXF2 RCLK TCLK EXEN2 C/T2# CP/RL2# Number Mnemonic Description Timer 2 overflow Flag Must be cleared by software. Set by hardware on Timer 2 overflow, if RCLK = 0 and TCLK = 0.
Page 54 Cleared to program P1.0/T2 as clock input or I/O port. Set to program P1.0/T2 as clock output. Down Counter Enable bit DCEN Cleared to disable Timer 2 as up/down counter. Set to enable Timer 2 as up/down counter. Reset Value = XXXX XX00b Not bit addressable AT89C5131A-L 4338F–USB–08/07...
Page 55: Programmable Counter Array (Pca)
AT89C5131A-L Programmable The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accu- Counter Array (PCA) racy. The PCA consists of a dedicated timer/counter which serves as the time base for an array of five compare/capture modules.
Page 56 / 4) CLK PERIPH PCA Enable Counter Overflow Interrupt Cleared to disable CF bit in CCON to inhibit an interrupt. Set to enable CF bit in CCON to generate an interrupt. Reset Value = 00XX X000b Not bit addressable AT89C5131A-L 4338F–USB–08/07...
Page 57 AT89C5131A-L The CMOD register includes three additional bits associated with the PCA (See Figure 28 and Table 48). • The CIDL bit allows the PCA to stop during idle mode. • The WDTE bit enables or disables the watchdog function on module 4.
Page 58 PCA counter and the module's capture/compare register. • The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge that a capture input will be active on. The CAPN bit enables the negative edge, and AT89C5131A-L 4338F–USB–08/07...
Page 59 AT89C5131A-L the CAPP bit enables the positive edge. If both bits are set both edges will be enabled and a capture will occur for either transition. • The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function.
Page 60 CCAPnH and CCAPnL and these are the registers that store the 16-bit count when a capture occurs or a compare should occur. When a module is used in the PWM mode these registers are used to control the duty cycle of the output (see Table 52 and Table 53) AT89C5131A-L 4338F–USB–08/07...
Page 61 AT89C5131A-L Table 52. CCAPnH Registers (n = 0-4) CCAP0H - PCA Module 0 Compare/Capture Control Register High (0FAh) CCAP1H - PCA Module 1 Compare/Capture Control Register High (0FBh) CCAP2H - PCA Module 2 Compare/Capture Control Register High (0FCh) CCAP3H - PCA Module 3 Compare/Capture Control Register High (0FDh)
Page 62: Pca Capture Mode
CCAPMn register. The PCA timer will be compared to the module's capture registers and when a match occurs an interrupt will occur if the CCFn (CCON SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set (see Figure 31). AT89C5131A-L 4338F–USB–08/07...
Page 63: High Speed Output Mode
AT89C5131A-L Figure 31. PCA Compare Mode and PCA Watchdog Timer CCON 0xD8 CCF4 CCF3 CCF2 CCF1 CCF0 Write to CCAPnL Reset PCA IT Write to CCAPnH CCAPnH CCAPnL Enable Match 16-bit Comparator RESET PCA Counter/Timer CCAPMn, n = 0 to 4...
Page 64: Pulse Width Modulator Mode
When CL overflows from FF to 00, CCAPLn is reloaded with the value in CCAPHn. This allows updating the PWM without glitches. The PWM and ECOM bits in the module's CCAPMn register must be set to enable the PWM mode. AT89C5131A-L 4338F–USB–08/07...
Page 65: Pca Watchdog Timer
AT89C5131A-L Figure 33. PCA PWM Mode CCAPnH Overflow CCAPnL “0” CEXn Enable < 8-bit Comparator ≥ “1” PCA Counter/Timer ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn CCAPMn, n = 0 to 4 0xDA to 0xDE PCA Watchdog Timer An on-board watchdog timer is available with the PCA to improve the reliability of the system without increasing chip count.
Page 66: Serial I/O Port
Serial I/O Port The serial I/O port in the AT89C5131A-L is compatible with the serial I/O port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as an Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (modes 1, 2 and 3).
Page 67: Automatic Address Recognition
AT89C5131A-L Figure 36. UART Timings in Modes 2 and 3 Start Data Byte Ninth Stop SMOD0 = 0 SMOD0 = 1 SMOD0 = 1 Automatic Address The automatic address recognition feature is enabled when the multiprocessor commu- nication feature is enabled (SM2 bit in SCON register is set).
Page 68 80C51 microcontrollers that do not support automatic address recognition. SADEN - Slave Address Mask Register (B9h) Reset Value = 0000 0000b Not bit addressable AT89C5131A-L 4338F–USB–08/07...
Page 69: Baud Rate Selection For Uart For Mode 1 And 3
AT89C5131A-L SADDR - Slave Address Register (A9h) Reset Value = 0000 0000b Not bit addressable Baud Rate Selection for The Baud Rate Generator for transmit and receive clocks can be selected separately via the T2CON and BDRCON registers. UART for Mode 1 and 3 Figure 37.
Page 70 The baud rate for UART is token by formula: SMOD1 CLK PERIPH Baud_Rate = (1-SPD) 2 x 6 x 16 x [256 - (BRL)] SMOD1 CLK PERIPH (BRL) = 256 (1-SPD) 2 x 6 x 16 x Baud_Rate AT89C5131A-L 4338F–USB–08/07...
Page 71 AT89C5131A-L Table 56. SCON Register – SCON Serial Control Register (98h) FE/SM0 Number Mnemonic Description Framing Error bit (SMOD0 = 1) Clear to reset the error state, not cleared by a valid stop bit. Set by hardware when an invalid stop bit is detected.
Page 72: Uart Registers
SADDR - Slave Address Register for UART (A9h) – – – – – – – – Reset Value = 0000 0000b SBUF - Serial Buffer Register for UART (99h) – – – – – – – – Reset Value = XXXX XXXXb AT89C5131A-L 4338F–USB–08/07...
Page 73 AT89C5131A-L BRL - Baud Rate Reload Register for the internal baud rate generator, UART (9Ah) – – – – – – – – Reset Value = 0000 0000b Table 57. T2CON Register T2CON - Timer 2 Control Register (C8h) EXF2...
Page 74 Cleared by hardware when interrupt or reset occurs. Set to enter idle mode. Reset Value = 00X1 0000b Not bit addressable Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesn’t affect the value of this bit. AT89C5131A-L 4338F–USB–08/07...
Page 75 AT89C5131A-L Table 59. BDRCON Register BDRCON - Baud Rate Control Register (9Bh) TBCK RBCK Number Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit Reserved The value read from this bit is indeterminate. Do not set this bit Reserved The value read from this bit is indeterminate.
Page 76: Interrupt System
Interrupt System Overview The AT89C5131A-L has a total of 11 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt, SPI interrupt, Keyboard interrupt, USB interrupt and the PCA global interrupt. These interrupts are shown in Figure 39.
Page 77: Registers
AT89C5131A-L Each of the interrupt sources can be individually enabled or disabled by setting or clear- ing a bit in the Interrupt Enable register (Table 61). This register also contains a global disable bit, which must be cleared to disable all interrupts at once.
Page 78 Cleared to disable timer 0 overflow interrupt. Set to enable timer 0 overflow interrupt. External interrupt 0 Enable bit Cleared to disable external interrupt 0. Set to enable external interrupt 0. Reset Value = 0000 0000b Bit addressable AT89C5131A-L 4338F–USB–08/07...
Page 79 AT89C5131A-L Table 62. IPL0 Register IPL0 - Interrupt Priority Register (B8h) PPCL PT2L PT1L PX1L PT0L PX0L Number Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. PCA interrupt Priority bit PPCL Refer to PPCH for priority level.
Page 80 External interrupt 1 Priority High bit PX1HPX1LPriority Level 0Lowest PX1H 1Highest Timer 0 overflow interrupt Priority High bit PT0HPT0LPriority Level 0Lowest PT0H 1Highest External interrupt 0 Priority High bit PX0HPX0LPriority Level 0Lowest PX0H 1Highest Reset Value = X000 0000b Not bit addressable AT89C5131A-L 4338F–USB–08/07...
Page 81 AT89C5131A-L Table 64. IEN1 Register IEN1 - Interrupt Enable Register (B1h) EUSB ESPI ETWI Number Mnemonic Description Reserved USB Interrupt Enable bit EUSB Cleared to disable USB interrupt. Set to enable USB interrupt. Reserved Reserved Reserved SPI interrupt Enable bit ESPI Cleared to disable SPI interrupt.
Page 82 SPI Interrupt Priority bit PSPIL Refer to PSPIH for priority level. TWI Interrupt Priority bit PTWIL Refer to PTWIH for priority level. Keyboard Interrupt Priority bit PKBL Refer to PKBH for priority level. Reset Value = X0XX X000b Not bit addressable AT89C5131A-L 4338F–USB–08/07...
Page 83 AT89C5131A-L Table 66. IPH1 Register IPH1 - Interrupt Priority High Register (B3h) PUSBH PSPIH PTWIH PKBH Number Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. USB Interrupt Priority High bit PUSBHPUSBLPriority Level...
Page 84: Interrupt Sources And Vector Addresses
0003h Timer 0 000Bh INT1 0013h Timer 1 001Bh UART RI+TI 0023h Timer 2 TF2+EXF2 002Bh CF + CCFn (n = 0-4) 0033h Keyboard KBDIT 003Bh TWIIT 0043h SPIIT 004Bh 0053h 005Bh 0063h UEPINT + USBINT 006Bh 0073h AT89C5131A-L 4338F–USB–08/07...
Page 85: Keyboard Interface
Keyboard Interface Introduction The AT89C5131A-L implements a keyboard interface allowing the connection of a 8 x n matrix keyboard. It is based on 8 inputs with programmable interrupt capability on both high or low level. These inputs are available as an alternate function of P1 and allow to exit from idle and power down modes.
Page 86: Registers
Set by hardware when the Port line 0 detects a programmed level. It generates a KBF0 Keyboard interrupt request if the KBIE.0 bit in KBIE register is set. Cleared by hardware when reading KBF SFR by software. Reset Value = 0000 0000b AT89C5131A-L 4338F–USB–08/07...
Page 87 AT89C5131A-L Table 69. KBE Register KBE - Keyboard Input Enable Register (9Dh) KBE7 KBE6 KBE5 KBE4 KBE3 KBE2 KBE1 KBE0 Number Mnemonic Description Keyboard line 7 Enable bit KBE7 Cleared to enable standard I/O pin. Set to enable KBF.7 bit in KBF register to generate an interrupt request.
Page 88 Set to enable a high level detection on Port line 1. Keyboard line 0 Level Selection bit KBLS0 Cleared to enable a low level detection on Port line 0. Set to enable a high level detection on Port line 0. Reset Value = 0000 0000b AT89C5131A-L 4338F–USB–08/07...
Page 89: Programmable Led
AT89C5131A-L Programmable LED AT89C5131A-L have up to 4 programmable LED current sources, configured by the register LEDCON. Table 71. LEDCON Register LEDCON (S:F1h) LED Control Register LED3 LED2 LED1 LED0 Number Mnemonic Description PortLED3Configuration 0Standard C51 Port LED3 1 2 mA current source when P3.7 is low 0 4 mA current source when P3.7 is low...
Page 90: Serial Peripheral Interface (Spi)
Each Slave peripheral is selected by one Slave Select pin (SS). This signal must stay low for any message for a Slave. It is obvious that only one Master (SS high level) can drive the network. The Master may select each Slave device by software through port AT89C5131A-L 4338F–USB–08/07...
Page 91 AT89C5131A-L pins (Figure 42). To prevent bus conflicts on the MISO line, only one slave should be selected at a time by the Master for a transmission. In a Master configuration, the SS line can be used in conjunction with the MODF flag in the SPI Status register (SPSTA) to prevent multiple masters from driving MOSI and SCK (see Section “Error Conditions”, page 95).
Page 92: Functional Description
When the Master device transmits data to the Slave device via the MOSI line, the Slave device responds by sending data to the Master device via the MISO line. This implies full-duplex transmission with both data out and data in synchronized with the same clock (Figure 44). AT89C5131A-L 4338F–USB–08/07...
Page 93 AT89C5131A-L Figure 44. Full-duplex Master/Slave Interconnection MISO MISO 8-bit Shift Register 8-bit Shift Register MOSI MOSI Clock Generator Master MCU Slave MCU Master Mode The SPI operates in Master mode when the Master bit, MSTR , in the SPCON register is set.
Page 94 SCK edge as a start transmission signal. The SS pin can remain low between transmis- sions (Figure 42). This format may be preferable in systems having only one Master and only one Slave driving the MISO data line. AT89C5131A-L 4338F–USB–08/07...
Page 95 AT89C5131A-L Error Conditions The following flags in the SPSTA signal SPI error conditions: Mode Fault (MODF) Mode Fault error in Master mode SPI indicates that the level on the Slave Select (SS) pin is inconsistent with the actual mode of the device. MODF is set to warn that there may have a multi-master conflict for system control.
Page 96 Set to have the SCK set to “1” in idle state. Clock Phase Cleared to have the data sampled when the SCK leaves the idle state (see CPHA CPOL). Set to have the data sampled when the SCK returns to idle state (see CPOL). AT89C5131A-L 4338F–USB–08/07...
Page 97 AT89C5131A-L Number Bit Mnemonic Description SPR2 SPR1 SPR0 Serial Peripheral Rate SPR1 000Reserved 00 1F CLK PERIPH/ 010 F CLK PERIPH/ 011F CLK PERIPH/ 100F CLK PERIPH/ 10 1F SPR0 CLK PERIPH/ 110F CLK PERIPH/ 1 11Reserved Reset Value = 0001 0100b...
Page 98 • Do not change SPR2, SPR1 and SPR0 • Do not change CPHA and CPOL • Do not change MSTR • Clearing SPEN would immediately disable the peripheral • Writing to the SPDAT will cause an overflow AT89C5131A-L 4338F–USB–08/07...
Page 99: Two Wire Interface (Twi)
AT89C5131A-L Two Wire Interface ( This section describes the 2-wire interface. The 2-wire bus is a bi-directional 2-wire serial communication standard. It is designed primarily for simple but efficient integrated circuit (IC) control. The system is comprised of two lines, SCL (Serial Clock) and SDA (Serial Data) that carry information between the ICs connected to them.
Page 100 Input Filter Output Stage SSDAT Shift Register Arbitration & Input Sink Logic Filter Timing & Control CLK PERIPH logic Interrupt Output Serial clock Stage generator Timer 1 overflow Control Register SSCON Status Status Decoder Bits SSCS Status Register AT89C5131A-L 4338F–USB–08/07...
Page 101: Description
AT89C5131A-L Description The CPU interfaces to the 2-wire logic via the following four 8-bit special function regis- ters: the Synchronous Serial Control register (SSCON; Table 86), the Synchronous Serial Data register (SSDAT; Table 87), the Synchronous Serial Control and Status reg- ister (SSCS;...
Page 102 When the slave address and the direction bit have been transmitted and an acknowl- edgement bit has been received, the serial interrupt flag is set again and a number of AT89C5131A-L 4338F–USB–08/07...
Page 103 AT89C5131A-L status code in SSCS are possible. There are 40h, 48h or 38h for the master mode and also 68h, 78h or B0h if the slave mode was enabled (AA=logic 1). The appropriate action to be taken for each of these status code is detailed in Table . This scheme is repeated until a STOP condition is transmitted.
Page 104: Notes
OSCA OSCA OSCA 62.5 53.5 71.5 62.5 Unused 133.3 266.6 Timer 1 in mode 2 can be used as TWI baudrate generator with the following 0.5 <. < 62.5 0.67 <. < 83 formula: 96.(256-”Timer1 reload value”) AT89C5131A-L 4338F–USB–08/07...
Page 105 AT89C5131A-L Figure 52. Format and State in the Master Transmitter Mode Successfull Data transmission to a slave receiver Next transfer started with a repeated start condition Not acknowledge received after the slave address Not acknowledge received after a data byte...
Page 106 SSSTO flag will be reset. Two-wire bus will be released and not addressed No SSDAT action slave mode will be entered. Arbitration lost in SLA+W or data bytes A START condition will be transmitted when the bus No SSDAT action becomes free. AT89C5131A-L 4338F–USB–08/07...
Page 107 AT89C5131A-L Figure 53. Format and State in the Master Receiver Mode Successfull Data transmission Data to a slave receiver Next transfer started with a repeated start condition Not acknowledge received after the slave address Arbitration lost in slave Other master...
Page 108 STOP condition will be transmitted and SSSTO flag Read data byte received; NOT ACK will be reset. has been returned STOP condition followed by a START condition will Read data byte be transmitted and SSSTO flag will be reset. AT89C5131A-L 4338F–USB–08/07...
Page 109 AT89C5131A-L Figure 54. Format and State in the Slave Receiver Mode Reception of the own P or S Data Data slave address and one or more data bytes. All are acknowledged. Last data byte received P or S is not acknowledged.
Page 110 Data byte will be received and NOT ACK will be Previously addressed with Read data byte or returned general call; data has been received; ACK has been Data byte will be received and ACK will be Read data byte returned returned AT89C5131A-L 4338F–USB–08/07...
Page 111 AT89C5131A-L Table 83. Status in Slave Receiver Mode (Continued) Application Software Response To/from SSDAT To SSCON Status Code Status of the 2-wire bus and (SSCS) 2-wire hardware Next Action Taken By 2-wire Software Switched to the not addressed slave mode; no...
Page 112 Last data byte will be transmitted and NOT ACK Load data byte or Data byte in SSDAT has been will be received transmitted; NOT ACK has Data byte will be transmitted and ACK will be been received Load data byte received AT89C5131A-L 4338F–USB–08/07...
Page 113 AT89C5131A-L Table 84. Status in Slave Transmitter Mode (Continued) Application Software Response To/from SSDAT To SSCON Status Code Status of the 2-wire bus and (SSCS) 2-wire hardware Next Action Taken By 2-wire Software Switched to the not addressed slave mode; no...
Page 114: Registers
Address bit 7 or Data bit 7. Address bit 6 or Data bit 6. Address bit 5 or Data bit 5. Address bit 4 or Data bit 4. Address bit 3 or Data bit 3. Address bit 2 or Data bit 2. AT89C5131A-L 4338F–USB–08/07...
Page 115 AT89C5131A-L Number Mnemonic Description Address bit 1 or Data bit 1. Address bit 0 (R/W) or Data bit 0. Table 88. SSCS (094h) Read - Synchronous Serial Control and Status Register Number Mnemonic Description Always zero Always zero Always zero...
Page 116: Usb Controller
The Universal Function Interface (UFI) realizes the interface between the data flow and the Dual Port RAM. Figure 56. USB Device Controller Block Diagram 48 MHz +/- 0.25% DPLL 12 MHz Microcontroller Interface D+/D- Buffer Up to 48 MHz UC_sysclk AT89C5131A-L 4338F–USB–08/07...
Page 117 AT89C5131A-L Serial Interface Engine (SIE) The SIE performs the following functions: • NRZI data encoding and decoding. • Bit stuffing and un-stuffing. • CRC generation and checking. • Handshakes. • TOKEN type identifying. • Address checking. • Clock generation (via DPLL).
Page 118 Figure 59. Minimum Intervention from the USB Device Firmware OUT Transactions: OUT DATA0 (n bytes) DATA1 DATA1 HOST interrupt C51 NACK Endpoint FIFO read (n bytes) IN Transactions: HOST DATA1 DATA1 NACK interrupt C51 Endpoint FIFO write Endpoint FIFO write AT89C5131A-L 4338F–USB–08/07...
Page 119: Configuration
AT89C5131A-L Configuration General Configuration • USB controller enable Before any USB transaction, the 48 MHz required by the USB controller must be correctly generated (See “Clock Controller” on page 13.). The USB controller will be then enabled by setting the EUSB bit in the USBCON register.
Page 120 Do not forget to select the correct endpoint number in the UEPNUM register before accessing to endpoint specific registers. Table 90. Summary of Endpoint Configuration Endpoint Configuration EPEN EPDIR EPTYPE UEPCONX Disabled 0XXX XXXb Control Bulk-in Bulk-out Interrupt-In Interrupt-Out Isochronous-In Isochronous-Out AT89C5131A-L 4338F–USB–08/07...
Page 121: Read/Write Data Fifo
AT89C5131A-L • Endpoint FIFO reset Before using an endpoint, its FIFO will be reset. This action resets the FIFO pointer to its original value, resets the byte counter of the endpoint (UBYCTLX and UBYCTHX registers), and resets the data toggle bit (DTGL bit in UEPCONX).
Page 122: Bulk/Interrupt Transactions
If the Host sends more bytes than supported by the endpoint FIFO, the overflow data won’t be stored, but the USB controller will consider that the packet is valid if the CRC is correct and the endpoint byte counter contains the number of bytes sent by the Host. AT89C5131A-L 4338F–USB–08/07...
Page 123 AT89C5131A-L Bulk/Interrupt OUT Figure 63. Bulk/Interrupt OUT Transactions in Ping-pong Mode Transactions in Ping-pong HOST Mode DATA0 (n Bytes) RXOUTB0 Endpoint FIFO Bank 0 - Read Byte 1 Endpoint FIFO Bank 0 - Read Byte 2 DATA1 (m Bytes) Endpoint FIFO Bank 0 - Read Byte n...
Page 124 The firmware will clear the TXCMPL bit before filling the endpoint FIFO with new data. The firmware will never write more bytes than supported by the endpoint FIFO. All USB retry mechanisms are automatically managed by the USB controller. AT89C5131A-L 4338F–USB–08/07...
Page 125 AT89C5131A-L Bulk/Interrupt IN Transactions Figure 65. Bulk/Interrupt IN Transactions in Ping-pong Mode in Ping-pong Mode HOST Endpoint FIFO Bank 0 - Write Byte 1 Endpoint FIFO Bank 0 - Write Byte 2 NACK Endpoint FIFO Bank 0 - Write Byte n...
Page 126: Control Transactions
Standard Mode” on page 124). To send a STALL handshake, see “STALL Handshake” on page 129. • For a Control Read transaction, the status stage consists of a OUT Zero Length Packet (see “Bulk/Interrupt OUT Transactions in Standard Mode” on page 122). AT89C5131A-L 4338F–USB–08/07...
Page 127: Isochronous Transactions
AT89C5131A-L Isochronous Transactions Isochronous OUT An endpoint will be first enabled and configured before being able to receive Isochro- Transactions in Standard nous packets. Mode When a OUT packet is received on an endpoint, the RXOUTB0 bit is set by the USB controller.
Page 128 Until the TXRDY bit has been set by the firmware for an endpoint bank, the USB controller won’t send anything at each IN requests concerning this bank. The firmware will never write more bytes than supported by the endpoint FIFO. AT89C5131A-L 4338F–USB–08/07...
Page 129: Miscellaneous
AT89C5131A-L Miscellaneous USB Reset The EORINT bit in the USBINT register is set by hardware when a End Of Reset has been detected on the USB bus. This triggers a USB interrupt if enabled. The USB con- troller is still enabled, but all the USB registers are reset by hardware. The firmware will clear the EORINT bit to allow the next USB reset detection.
Page 130: Suspend/Resume Management
0 the SUSPCLK bit in the USBCON register if needed. The firmware has to clear the SPINT bit in the USBINT register before any other USB operation in order to wake up the USB controller from its Suspend mode. The USB controller is then re-activated. AT89C5131A-L 4338F–USB–08/07...
Page 131 AT89C5131A-L Figure 66. Example of a Suspend/Resume Management USB Controller Init SPINT Detection of a SUSPEND State Clear SPINT Set SUSPCLK Disable PLL microcontroller in Power-down WUPCPU Detection of a RESUME State Enable PLL Clear SUSPCLK Clear WUPCPU Bit 4338F–USB–08/07...
Page 132 Figure 67. Example of REMOTE WAKEUP Management USB Controller Init SET_FEATURE: DEVICE_REMOTE_WAKEUP Set RMWUPE SPINT Detection of a SUSPEND State Suspend Management Need USB Resume Enable Clocks Clear SPINT UPRSM = 1 Set SDMWUP UPRSM Upstream RESUME Sent Clear SDRMWUP AT89C5131A-L 4338F–USB–08/07...
Page 133: Detach Simulation
AT89C5131A-L Detach Simulation In order to be re-enumerated by the Host, the AT89C5131A-L has the possibility to sim- ulate a DETACH - ATTACH of the USB bus. The V output voltage is between 3.0V and 3.6V. This output can be connected to the D+ pull-up as shown in Figure 68.
Page 134 USB resume is detected on the USB bus, after a SUSPEND state. • SPINT: Suspend Interrupt (See “USBIEN Register USBIEN (S:BEh) USB Global Interrupt Enable Register” on page 138.). This bit is set by hardware when a USB suspend is detected on the USB bus. AT89C5131A-L 4338F–USB–08/07...
Page 135 AT89C5131A-L Figure 71. USB Interrupt Control Block Diagram Endpoint X (X = 0..6) TXCMP UEPSTAX.0 RXOUTB0 UEPSTAX.1 RXOUTB1 EPXINT UEPSTAX.6 UEPINT.X EPXIE RXSETUP UEPIEN.X UEPSTAX.2 STLCRC UEPSTAX.3 WUPCPU EUSB USBINT.5 IE1.6 EWUPCPU USBIEN.5 EORINT USBINT.4 EEORINT USBIEN.4 SOFINT USBINT.3 ESOFINT USBIEN.3...
Page 136: Usb Registers
It will not be cleared afterwards by the device firmware. It is cleared by hardware on hardware reset or when an USB reset is received (see above). When this bit is cleared, the default function address is used (0). Reset Value = 00h AT89C5131A-L 4338F–USB–08/07...
Page 137 AT89C5131A-L Table 93. USBINT Register USBINT (S:BDh) USB Global Interrupt Register WUPCPU EORINT SOFINT SPINT Bit Number Mnemonic Description Reserved The value read from these bits is always 0. Do not set these bits. Wake Up CPU Interrupt This bit is set by hardware when the USB controller is in SUSPEND state and is re-activated by a non-idle signal FROM USB line (not by an upstream resume).
Page 138 Cleared this bit to disable the function. USB Address This field contains the default address (0) after power-up or USB bus reset. UADD[6:0] It will be written with the value set by a SET_ADDRESS request received by the device firmware. Reset Value = 80h AT89C5131A-L 4338F–USB–08/07...
Page 139 AT89C5131A-L Table 96. UEPNUM Register UEPNUM (S:C7h) USB Endpoint Number EPNUM3 EPNUM2 EPNUM1 EPNUM0 Bit Number Bit Mnemonic Description Reserved The value read from these bits is always 0. Do not set these bits. Endpoint Number Set this field with the number of the endpoint which will be accessed when...
Page 140 10Bulk endpoint 11Interrupt endpoint Note: 1. (X = EPNUM set in UEPNUM Register UEPNUM (S:C7h) USB Endpoint Number) Reset Value = 80h when UEPNUM = 0 (default Control Endpoint) Reset Value = 00h otherwise for all other endpoints AT89C5131A-L 4338F–USB–08/07...
Page 141 AT89C5131A-L Table 98. UEPSTAX (S:CEh) USB Endpoint X Status Register RXOUTB1 STALLRQ TXRDY STL/CRC RXSETUP RXOUTB0 TXCMP Bit Number Mnemonic Description Control Endpoint Direction This bit is used only if the endpoint is configured in the control type (seeSection “UEPCONX Register UEPCONX (S:D4h) USB Endpoint X Control Register”).
Page 142 Byte Count High Register X (X = EPNUM set in UEPNUM Register UEPNUM (S:C7h) USB Endpoint Number) (see Figure 100 on page 142). This byte count is equal to the number of data bytes received after the Data PID. (S:C7h) USB Endpoint Number) Reset Value = 00h AT89C5131A-L 4338F–USB–08/07...
Page 143 AT89C5131A-L Table 101. UBYCTHX Register UBYCTHX (S:E3h) USB Byte Count High Register X (X = EPNUM set in UEPNUM Register UEPNUM BYCT9 BYCT8 Bit Number Bit Mnemonic Description Reserved The value read from these bits is always 0. Do not set these bits.
Page 144 Set this bit and reset the endpoint FIFO prior to any other operation, upon EP0RST hardware reset or when an USB bus reset has been received. Then, clear this bit to complete the reset operation and start using the FIFO. Reset Value = 00h AT89C5131A-L 4338F–USB–08/07...
Page 145 AT89C5131A-L Table 103. UEPINT Register UEPINT (S:F8h read-only) USB Endpoint Interrupt Register EP6INT EP5INT EP4INT EP3INT EP2INT EP1INT EP0INT Bit Number Mnemonic Description Reserved The value read from this bit is always 0. Do not set this bit. Endpoint 6 Interrupt This bit is set by hardware when an endpoint interrupt source has been detected on the endpoint 6.
Page 146 Clear this bit to disable the interrupts for this endpoint. Endpoint 0 Interrupt Enable EP0INTE Set this bit to enable the interrupts for this endpoint. Clear this bit to disable the interrupts for this endpoint. Reset Value = 00h AT89C5131A-L 4338F–USB–08/07...
Page 147 AT89C5131A-L Table 105. UFNUMH Register UFNUMH (S:BBh, read-only) USB Frame Number High Register CRCOK CRCERR FNUM10 FNUM9 FNUM8 Number Mnemonic Description Frame Number CRC OK This bit is set by hardware when a new Frame Number in Start of Frame Packet CRCOK is received without CRC error.
Page 148: Reset
V as shown in Figure 73. Resistor value and input characteristics are discussed in the Section “DC Characteristics” of the AT89C5131A-L datasheet. Figure 73. Reset Circuitry and Power-On Reset To internal reset a. RST input circuitry b.
Page 149: Reset Output
AT89C5131A-L Reset Output As detailed in Section “Hardware Watchdog Timer”, page 155, the WDT generates a 96- clock period pulse on the RST pin. In order to properly propagate this pulse to the rest of the application in case of external capacitor or power-supply supervisor circuit, a 1 kΩ...
Page 150: Power Monitor
Power Fail Detect threshold level, the Reset will be applied immediately. The Voltage regulator generates a regulated internal supply for the CPU core the mem- ories and the peripherals. Spikes on the external Vcc are smoothed by the voltage regulator. AT89C5131A-L 4338F–USB–08/07...
Page 151 AT89C5131A-L The Power fail detect monitor the supply generated by the voltage regulator and gener- ate a reset if this supply falls below a safety threshold as illustrated in the Figure 76 below. Figure 76. Power Fail Detect Reset When the power is applied, the Power Monitor immediately asserts a reset. Once the internal supply after the voltage regulator reach a safety level, the power monitor then looks at the XTAL clock input.
Page 152: Power Management
In this case, the higher priority interrupt service routine is executed. Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction that put AT89C5131A-L into power-down mode. AT89C5131A-L...
Page 153 AT89C5131A-L Figure 77. Power-down Exit Waveform INT0 INT1 XTAL Power-down Phase Oscillator restart Phase Active Phase Active Phase Exit from power-down by reset redefines all the SFRs, exit from power-down by external interrupt does no affect the SFRs. Exit from power-down by either reset or external interrupt does not affect the internal RAM content.
Page 154: Registers
Power-down mode bit Set this bit to enter in power-down mode. Cleared by hardware when reset occurs. Idle mode bit Set this bit to enter in Idle mode. Cleared by hardware when interrupt or reset occurs. Reset Value = 10h AT89C5131A-L 4338F–USB–08/07...
Page 155: Hardware Watchdog Timer
AT89C5131A-L Hardware Watchdog The WDT is intended as a recovery method in situations where the CPU may be sub- jected to software upset. The WDT consists of a 14-bit counter and the WatchDog Timer Timer ReSeT (WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H.
Page 156: Wdt During Power-Down And Idle
In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the AT89C5131A-L while in Idle mode, the user should always set up a timer that will peri- odically exit Idle, service the WDT, and re-enter Idle mode.
Page 157: Once Mode (On Chip Emulation)
• Hold ALE low as RST is deactivated. While the AT89C5131A-L is in ONCE mode, an emulator or test CPU can be used to drive the circuit Table 111 shows the status of the port pins during ONCE mode. Normal operation is restored when normal reset is applied.
Page 158: Reduced Emi Mode
Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if X2 mode is used) (default). Set , ALE is active only during a MOVX or MOVC instruction is used. Reset Value = 0X0X 1100b Not bit addressable AT89C5131A-L 4338F–USB–08/07...
Page 159: Electrical Characteristics
AT89C5131A-L Electrical Characteristics Absolute Maximum Ratings Note: Stresses at or above those listed under “Absolute Ambient Temperature Under Bias: Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional I = industrial ............-40°C to 85°C operation of the device at these or any other condi- Storage Temperature ........
Page 160 V may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. Figure 78. I Test Condition, Active Mode (NC) XTAL2 CLOCK XTAL1 SIGNAL All other pins are disconnected. AT89C5131A-L 4338F–USB–08/07...
Page 161 AT89C5131A-L Figure 79. I Test Condition, Idle Mode (NC) XTAL2 CLOCK XTAL1 SIGNAL All other pins are disconnected. Figure 80. I Test Condition, Power-down Mode (NC) XTAL2 XTAL1 All other pins are disconnected. Figure 81. Clock Signal Waveform for I Tests in Active and Idle Modes -0.5V...
Page 162: Usb Dc Parameters
USB Reference Voltage Input High Voltage for D+ and D- (Driven) Input High Voltage for D+ and D- (Floating) Input Low Voltage for D+ and D- Output High Voltage for D+ and D- Output Low Voltage for D+ and D- AT89C5131A-L 4338F–USB–08/07...
Page 163: Ac Parameters
AT89C5131A-L AC Parameters Explanation of the AC Each timing symbol has 5 characters. The first character is always a “T” (stands for Symbols time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for.
Page 164 LLPL 3 T - x 1.5 T - x PLPH 3 T - x 1.5 T - x PLIV PXIX T - x 0.5 T - x PXIZ 5 T - x 2.5 T - x AVIV PLAZ AT89C5131A-L 4338F–USB–08/07...
Page 165 AT89C5131A-L External Program Memory Read Cycle 12 T CLCL LHLL LLIV LLPL PLPH PSEN PXAV LLAX PXIZ PLIV AVLL TPLAZ PXIX PORT 0 INSTR IN A0-A7 INSTR IN A0-A7 INSTR IN AVIV ADDRESS PORT 2 ADDRESS A8-A15 ADDRESS A8-A15 OR SFR-P2 External Data Memory Table 117.
Page 166 Table 118. AC Parameters for a Variable Clock (F = 40 MHz) Symbol Units RLRH WLWH RLDV RHDX RHDZ LLDV AVDV LLWL AVWL QVWX QVWH WHQX RLAZ WHLH AT89C5131A-L 4338F–USB–08/07...
Page 167 AT89C5131A-L Table 119. AC Parameters for a Variable Clock Standard Symbol Type Clock X2 Clock X Parameter Units 6 T - x 3 T - x RLRH 6 T - x 3 T - x WLWH 5 T - x 2.5 T - x...
Page 168 Symbol Type Clock X2 Clock for -M Range Units 12 T XLXL 10 T - x 5 T - x QVHX 2 T - x T - x XHQX XHDX 10 T - x 5 T- x XHDV AT89C5131A-L 4338F–USB–08/07...
Page 169 AT89C5131A-L Shift Register Timing Waveform INSTRUCTION XLXL CLOCK XHQX QVXH OUTPUT DATA SET TI XHDX WRITE to SBUF XHDV INPUT DATA VALID VALID VALID VALID VALID VALID VALID VALID SET RI CLEAR RI External Clock Drive Table 123. AC Parameters...
Page 170 For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded V level occurs. I ≥ ±20 mA. AT89C5131A-L 4338F–USB–08/07...
Page 171 AT89C5131A-L Clock Waveforms Valid in normal clock mode. In X2 mode XTAL2 must be changed to XTAL2/2. STATE4 STATE5 STATE6 STATE1 STATE2 STATE3 STATE4 STATE5 INTERNAL CLOCK XTAL2 THESE SIGNALS ARE NOT ACTIVATED DURING THE EXECUTION OF A MOVX INSTRUCTION...
Page 172 Configuration bits (fuses bits) memory write Cycles cycles (BLJB, X2, OSCON0, OSCON1) EEPROM Data memory write cycles 100K Cycles Figure 82. Flash Memory - ISP Waveforms SVRL RLSX PSEN1 Figure 83. Flash Memory - Internal Busy Waveforms FBUSY bit BHBL AT89C5131A-L 4338F–USB–08/07...
Page 173: Usb Ac Parameters
AT89C5131A-L USB AC Parameters Rise Time Fall Time Hmin Lmax Differential Data Lines Table 126. USB AC Parameters Symbol Parameter Unit Test Conditions Rise Time Fall Time Full-speed Data Rate 11.9700 12.0300 Mb/s FDRATE Crossover Voltage Source Jitter Total to Next -3.5...
Page 174 Output Data Valid after Clock Edge CLOV, CHOV Output Data Hold Time after Clock Edge CLOX CHOX Note: is XTAL period when SPI interface operates in X2 mode or twice XTAL period when SPI inter- face operates in X1 mode. AT89C5131A-L 4338F–USB–08/07...
Page 175 AT89C5131A-L Waveforms Figure 84. SPI Slave Waveforms (CPHA= 0) (input) CLSH SLCH SLCL CHCH CHSH SHSL CLCH (CPOL= 0) (input) CHCX CLCX CHCL (CPOL= 1) (input) CLOX CLOV SLOV SHOX CHOX CHOV MISO SLAVE MSB OUT BIT 6 SLAVE LSB OUT...
Page 176 (CPOL= 1) (output) IVCH CHIX IVCL CLIX MOSI MSB IN BIT 6 LSB IN (input) CLOV CLOX CHOX CHOV MISO Port Data MSB OUT BIT 6 LSB OUT Port Data (output) handled by software using general purpose port pin. AT89C5131A-L 4338F–USB–08/07...
Page 177: Ordering Information
Tray AT89C5131A-S3SUL 3.0 to 3.6V Industrial & Green PLCC52 Stick AT89C5131A-TISUL 3.0 to 3.6V Industrial & Green SO28 Stick Note: 1. Optional Packing and Package options (please consult Atmel sales representative): -Tape and Reel -Dry Pack -Known good dice 4338F–USB–08/07...
Page 178: Packaging Information
Packaging Information 64-lead VQFP AT89C5131A-L 4338F–USB–08/07...
Page 179: 52-Lead Plcc
AT89C5131A-L 52-lead PLCC STANDARD NOTES FOR PLCC: 1/ CONTROLLING DIMENSIONS : INCHES 2/ DIMENSIONING AND TOLERANCING PER ANSI Y 14.5M - 1982. 3/ "D" AND "E1" DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTUSIONS. MOLD FLASH OR PROTUSIONS SHALL NOT EXCEED 0.20 mm (.008 INCH) PER SIDE.
Page 180 28-lead SO AT89C5131A-L 4338F–USB–08/07...
Page 181 AT89C5131A-L Document Revision History Changes from 1. Correction to Figure 4 on page 11. 4338D - 09/05 to 4338E - 06/06 Changes from 1. Hardware Conditions section Page 45 changed to recommend the use of 1K pull-up between PSEN and GND in ISP mode.
Page 182: Table Of Contents
Flash Registers and Memory Map..............37 Flash Memory Status..................40 Memory Organization ..................40 EEPROM Data Memory............... 41 Description......................41 Write Data in the Column Latches ..............41 Programming ...................... 41 Read Data......................41 Registers......................42 In-System Programming (ISP) ............43 AT89C5131A-L 4338F–USB–08/07...
Page 183 AT89C5131A-L Flash Programming and Erasure................ 43 Boot Process ...................... 44 Application-Programming-Interface ..............45 XROW Bytes....................... 45 Hardware Conditions ..................45 On-chip Expanded RAM (ERAM)............47 Timer 2 ....................50 Auto-reload Mode ....................50 Programmable Clock Output ................51 Programmable Counter Array (PCA) ..........55 PCA Capture Mode.....................
Page 184 DC Parameters ....................159 USB DC Parameters..................162 AC Parameters ....................163 USB AC Parameters..................173 SPI Interface AC Parameters ................173 Ordering Information ................ 177 Packaging Information ..............178 64-lead VQFP ....................178 52-lead PLCC ....................179 AT89C5131A-L 4338F–USB–08/07...
Page 185 AT89C5131A-L 28-lead SO......................180 Document Revision History ............. 181 Changes from 4338D - 09/05 to 4338E - 06/06..........181 Changes from 4338E - 06/06 to 4338F - 08/07 ..........181 4338F–USB–08/07...
Page 186 Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY...

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