ARTERY AT32F405 Series Manuals

Manuals and User Guides for ARTERY AT32F405 Series. We have 2 ARTERY AT32F405 Series manuals available for free PDF download: Reference Manual, Getting Started

ARTERY AT32F405 Series Reference Manual (516 pages)

ARM-based 32-bit Cortex -M4F MCU+FPU, with 128 to 256 KB Flash, sLib, USBFS/HS-OTG, 12 timers, 1 ADC, 20 communication interfaces

Brand: ARTERY | Category: Computer Hardware | Size: 14 MB

Table of Contents
2
System Architecture
33
System Overview
34
ARM Cortex -M4F Processor
34
Bit Band
34
Table 1-1 Bit-Band Address Mapping in SRAM
35
Interrupt and Exception Vectors
36
Table 1-2 Bit-Band Address Mapping in the Peripheral Area
36
Table 1-3 AT32F402/405 Series Vector Table
36
System Tick (Systick)
40
Reset
40
List of Abbreviations for Registers
41
Table 1-4 List of Abbreviations for Registers
41
Device Characteristics Information
42
Flash Memory Size Register
42
Device Electronic Signature
42
Table 1-5 Base Address and Reset Value of Registers
42
Memory Resources
43
Internal Memory Address Map
43
Figure 2-1 AT32F402/405 Address Mapping
43
Flash Memory
44
Table 2-1 Flash Memory Organization (256 KB)
44
Table 2-2 Flash Memory Organization (128 KB)
44
SRAM Memory
45
Peripheral Address Map
45
Table 2-3 Peripheral Boundary Address
45
Power Control (PWC)
48
Introduction
48
Main Features
48
Figure 3-1 Block Diagram of each Power Supply
48
Por/Lvr
49
Power Voltage Monitor (PVM)
49
Figure 3-2 Power-On/Low Voltage Reset Waveform
49
Figure 3-3 PVM Threshold and Output
49
Power Domain
50
Power Saving Modes
50
PWC Registers
52
Power Control Register (PWC_CTRL)
52
Table 3-1 PWC Register Map and Reset Values
52
Power Control/Status Register (PWC_CTRLSTS)
53
LDO Output Voltage Select Register (PWC_LDOOV)
55
Clock and Reset Manage (CRM)
56
Clock
56
Figure 4-1 AT32F405 Clock Tree
56
Clock Sources
57
Figure 4-2 AT32F402 Clock Tree
57
System Clock
58
Peripheral Clock
58
Clock Fail Detector
58
Auto Step-By-Step System Clock Switch
59
Internal Clock Output
59
Interrupts
59
Reset
59
System Reset
59
Figure 4-3 System Reset Circuit
59
Battery Powered Domain Reset
60
CRM Registers
60
Clock Control Register (CRM_CTRL)
60
Table 4-1 CRM Register Map and Reset Values
60
PLL Clock Configuration Register (CRM_PLLCFG)
62
Clock Configuration Register (CRM_CFG)
63
Clock Interrupt Register (CRM_CLKINT)
64
AHB Peripheral Reset Register 1 (CRM_AHBRST1)
65
AHB Peripheral Reset Register 2 (CRM_AHBRST2)
67
AHB Peripheral Reset Register 3 (CRM_AHBRST3)
67
APB1 Peripheral Reset Register (CRM_APB1RST)
67
APB2 Peripheral Reset Register (CRM_APB2RST)
68
AHB Peripheral Clock Enable Register 1 (CRM_AHBEN1)
69
AHB Peripheral Clock Enable Register 2 (CRM_AHBEN2)
69
AHB Peripheral Clock Enable Register 3 (CRM_AHBEN3)
70
APB1 Peripheral Clock Enable Register (CRM_APB1EN)
70
APB2 Peripheral Clock Enable Register (CRM_APB2EN)
71
AHB Peripheral Clock Enable in Low-Power Mode Register 1 (CRM_AHBLPEN1)
72
AHB Peripheral Clock Enable in Low-Power Mode Register
72
Crm_Ahblpen2)
72
Crm_Ahblpen3)
73
APB1 Peripheral Clock Enable in Low -Power Mode Register
73
(Crm_Apb1Lpen)
73
APB2 Peripheral Clock Enable in Low-Power Mode Register
74
(Crm_Apb2Lpen)
74
Battery Powered Domain Control Register (CRM_BPDC)
75
Control/Status Register (CRM_CTRLSTS)
75
OTGHS Control Register (CRM_OTGHS)
76
Additional Register 1 (CRM_MISC1)
76
Additional Register 2 (CRM_MISC2)
77
Flash Memory Controller (FLASH)
79
FLASH Introduction
79
Table 5-1 Flash Memory Architecture (256 KB)
79
Table 5-2 Flash Memory Architecture (128 KB)
79
Table 5-3 User System Data Area
80
Flash Memory Operation
81
Unlock/Lock
81
Erase Operation
81
Figure 5-1 Flash Memory Sector Erase Process
82
Programming Operation
83
Figure 5-2 Flash Memory Mass Erase Process
83
Figure 5-3 Flash Memory Programming Process
84
Read Operation
85
Main Flash Memory Extension Area
85
User System Data Area Operation
85
Unlock/Lock
85
Erase Operation
85
Programming Operation
86
Figure 5-4 System Data Area Erase Process
86
Read Operation
87
Flash Memory Protection
87
Access Protection
87
Figure 5-5 System Data Area Programming Process
87
Erase/Program Protection
88
Table 5-4 Flash Memory Access Limit
88
Read Access
89
Special Functions
89
Security Library Settings
89
Boot Memory Used as Flash Memory Extension
90
CRC Verify
90
FLASH Registers
90
Table 5-5 Flash Memory Register Map and Reset Value
90
Flash Performance Select Register (FLASH_PSR)
91
Flash Unlock Register (FLASH_UNLOCK)
91
Flash User System Data Unlock Register (FLASH_USD_UNLOCK)
92
Flash Status Register (FLASH_STS)
92
Flash Control Register (FLASH_CTRL)
92
Flash Address Register (FLASH_ADDR)
93
User System Data Register (FLASH_USD)
93
Erase/Program Protection Status Register (FLASH_EPPS)
93
Flash Security Library Status Register 0 (SLIB_STS0)
93
Flash Security Library Status Register 1 (SLIB_STS1)
94
Security Library Password Clear Register (SLIB_PWD_CLR)
94
Security Library Additional Status Register (SLIB_MISC_STS)
95
Flash CRC Address Register (FLASH_CRC_ADDR)
95
Flash CRC Check Control Register (FLASH_CRC_CTRL)
95
Flash CRC Check Result Register (FLASH_CRC_CHKR)
95
Security Library Password Setting Register (SLIB_SET_PWD)
96
Security Library Address Setting Register (SLIB_SET_RANGE)
96
Flash Extension Memory Security Library Setting Register
97
(Em_Slib_Set)
97
Boot Memory Mode Setting Register (BTM_MODE_SET)
97
Security Library Unlock Register (SLIB_UNLOCK)
97
Gpios and IOMUX
98
Introduction
98
Function Overview
98
GPIO Structure
98
Figure 6-1 GPIO Basic Structure
98
GPIO Reset Status
99
General-Purpose Input Configuration
99
Analog Input/Output Configuration
99
General-Purpose Output Configuration
99
I/O Port Protection
100
IOMUX Structure
100
Multiplexed Function Pull-Up/Pull-Down Configuration
100
Figure 6-2 IOMXU Structure
100
IOMUX Input/Output
101
Table 6-1 Port a Multiplexed Function Configuration with GPIOA_MUX* Register
101
Table 6-2 Port B Multiplexed Function Configuration with GPIOB_MUX* Register
103
Table 6-3 Port C Multiplexed Function Configuration with GPIOC_MUX* Register
105
Table 6-4 Port D Multiplexed Function Configuration with GPIOD_MUX* Register
107
Table 6-5 Port F Multiplexed Function Configuration with GPIOF_MUX* Register
107
Peripheral MUX Function Configuration
108
IOMUX Mapping Priority
108
External Interrupt/Wake-Up Lines
108
Table 6-6 Pins Owned by Hardware
108
GPIO Registers
109
GPIO Configuration Register (Gpiox_Cfgr) (X=A
109
GPIO Output Mode Register (Gpiox_Omode) (X=A
109
Table 6-7 GPIO Register Map and Reset Values
109
GPIO Drive Capability Register (Gpiox_Odrvr) (X=A..f
110
GPIO Pull-Up/Pull-Down Register (Gpiox_Pull) (X=A..f
110
GPIO Input Data Register (Gpiox_Idt) (X=A..f
110
GPIO Output Data Register (Gpiox_Odt) (X=A..f
110
GPIO Set/Clear Register (Gpiox_Scr) (X=A..f
110
GPIO Write Protection Register (Gpiox_Wpr) (X=A..f
111
GPIO Multiplexed Function Low Register (Gpiox_Muxl) (X=A
111
GPIO Multiplexed Function High Register (Gpiox_Muxh) (X=A
112
GPIO Port Bit Clear Register (Gpiox_Clr) (X=A..f
112
GPIO Port Bit Toggle Register (Gpiox_Togr) (X=A..f
113
GPIO Huge Current Control Register (Gpiox_Hdrv) (X=A
113
System Configuration Controller (SYSCFG)
114
Introduction
114
SCFG Registers
114
SCFG Configuration Register 1 (SCFG_CFG1)
114
SCFG Configuration Register 2 (SCFG_CFG2)
114
Table 7-1 SCFG Register Map and Reset Value
114
SCFG External Interrupt Configuration Register 1 (SCFG_EXINTC1)
115
External Interrupt/Event Controller (EXINT)
119
EXINT Introduction
119
Function Overview and Configuration Procedure
119
Figure 8-1 External Interrupt/Event Controller Block Diagram
119
EXINT Registers
120
Interrupt Enable Register (EXINT_INTEN)
120
Event Enable Register (EXINT_EVTEN)
120
Polarity Configuration Register 1 (EXINT_POLCFG1)
120
Polarity Configuration Register 2 (EXINT_POLCFG2)
120
Table 8-1 External Interrupt/Event Controller Register Map and Reset Value
120
Software Trigger Register (EXINT_SWTRG)
121
Interrupt Status Register (EXINT_INTSTS)
121
DMA Controller (DMA)
122
Introduction
122
Main Features
122
Figure 9-1 DMA Block Diagram
122
Function Overview
123
DMA Configuration
123
Handshake Mechanism
123
Arbiter
123
Figure 9-2 Re-Arbitrate after Request/Acknowledge
123
Programmable Data Transfer Width
124
Figure 9-3 PWIDTH: Byte, MWIDTH: Half-Word
124
Figure 9-4 PWIDTH: Half-Word, MWIDTH: Word
124
Figure 9-5 PWIDTH: Word, MWIDTH: Byte
124
Errors
125
Interrupts
125
DMA Multiplexer (DMAMUX)
125
DMAMUX Function Overview
125
Figure 9-6 DMAMUX Block Diagram
125
Table 9-1 DMA Error Event
125
Table 9-2 DMA Interrupts
125
Table 9-3 Flexible DMA1 / DMA2 Request Mapping
126
DMAMUX Overflow Interrupts
127
Figure 9-7 DMAMUX Request Synchronized Mode
127
Table 9-4 DMAMUX EXINT LINE for Trigger Input and Synchronized Input
127
DMA Registers
128
Figure 9-8 DMAMUX Event Generation
128
Table 9-5 DMA Register Map and Reset Value
128
DMA Interrupt Status Register (DMA_STS)
130
DMA Interrupt Flag Clear Register (DMA_CLR)
132
DMA Channel-X Configuration Register (Dma_Cxctrl) (X=1
134
DMA Channel-X Number of Data Register (Dma_Cxdtcnt) (X=1
135
DMA Channel-X Peripheral Address Register (Dma_Cxpaddr)
135
DMA Channel-X Memory Address Register (Dma_Cxmaddr
135
DMAMUX Select Register (DMA_MUXSEL)
135
DMAMUX Channel-X Control Register (Dma_Muxcxctrl
136
DMAMUX Channel Synchronization Status Register
137
(Dma_Muxsyncsts)
137
DMAMUX Generator Interrupt Status Register (DMA_MUXGSTS)
138
CRC Calculation Unit (CRC)
139
CRC Introduction
139
CRC Function Description
139
Figure10-1 CRC Calculation Unit Block Diagram
139
CRC Registers
140
Data Register (CRC_DT)
140
Common Data Register (CRC_CDT)
140
Table 10-1 CRC Register Map and Reset Value
140
Control Register (CRC_CTRL)
141
Initialization Register (CRC_IDT)
141
Polynomial Register (CRC_POLY)
141
C Interface
142
C Introduction
142
C Main Features
142
C Function Overview
142
Figure 11-1 I C Bus Protocol
142
I 2 C Interface
143
Figure 11-2 I 2 C Interface Block Diagram
143
C Timing Control
145
Figure 11-3 Setup and Hold Time
145
Data Transfer Management
146
Table 11-1 I 2 C Timing Specifications
146
I 2 C Master Communication Flow
147
Table 11-2 I C Configuration
147
Figure 11-4 I 2 C Master Transmission Flow
149
Figure 11-5 Transfer Sequence of I
150
Figure 11-6 I 2 C Master Receive Flow
150
Figure 11-7 Transfer Sequence of I
151
Figure 11-8 10-Bit Address Read Access When READH10=1
151
Figure 11-9 10-Bit Address Read Access When READH10=0
151
I 2 C Slave Communication Flow
152
Figure 11-10 I 2 C Slave Transmission Flow
153
Figure 11-11 I 2 C Slave Transmission Timing
154
Figure 11-12 I 2 C Slave Receive Flow
154
Smbus
155
Figure 11-13 I 2 C Slave Receive Timing
155
Table 11-3 Smbus Timeout Specification
156
Smbus Master Communication Flow
157
Table 11-4 Smbus Timeout Detection Configuration
157
Table 11-5 Smbus Mode Configuration
157
Figure 11-14 Smbus Master Transmission Timing
158
Smbus Slave Communication Flow
159
Figure 11-15 Smbus Master Receive Timing
159
Figure 11-16 Smbus Slave Transmission Flow
161
Figure 11-17 Smbus Slave Transmission Timing
161
Figure 11-18 Smbus Slave Receive Flow
162
Data Transfer Using DMA
163
Figure 11-19 Smbus Slave Receive Timing
163
Error Management
164
Table 11-6 I 2 C Error Events
164
C Interrupt Requests
165
C Debug Mode
165
C Registers
165
Table 11-7 I 2 C Interrupt Requests
165
Table 11-8 I 2 C Register Map and Reset Value
165
Control Register 1 (I2C_CTRL1)
166
Control Register 2 (I2C_CTRL2)
167
Address Register 1 (I2C_OADDR1)
167
Address Register 2 (I2C_OADDR2)
167
Timing Register (I2C_CLKCTRL)
168
Timeout Register (I2C_TIMEOUT)
168
Status Register (I2C_STS)
168
Status Clear Flag (I2C_CLR)
170
PEC Register (I2C_PEC)
170
Receive Data Register (I2C_RXDT)
170
Transmit Data Register (I2C_TXDT)
170
Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
171
USART Introduction
171
Figure 12-1 USART Block Diagram
171
Full-Duplex/Half-Duplex Selector
173
Mode Selector
173
Introduction
173
Configuration Procedure
173
Figure 12-2 BFF and FERR Detection in LIN Mode
173
Figure 12-3 Smartcard Frame Format
174
Figure 12-4 Irda DATA(3/16) - Normal Mode
174
Figure 12-5 Hardware Flow Control
175
USART Frame Format and Configuration
176
Figure 12-6 Mute Mode Using Idle Line or Address Mark Detection
176
Figure 12-7 8-Bit Format USART Synchronous Mode
176
Figure 12-8 Word Length Configuration
177
DMA Transfer Introduction
178
Transmission Using DMA
178
Figure 12-9 Stop Bit Configuration
178
Reception Using DMA
179
Baud Rate Generation
179
Introduction
179
Configuration
179
Table 12-1 Error Calculation for Programmed Baud Rate
179
Transmitter
180
Introduction
180
Transmitter Configuration
180
Figure 12-10 Variations When Transmitting TDC/TDBE
180
Receiver
181
Introduction
181
Receiver Configuration
181
Start Bit and Noise Detection
182
Table 12-2 Data Sampling over Start Bit and Noise Detection
182
Table 12-3 Data Sampling over Valid Data and Noise Detection
182
Tx/Rx Swap
183
Figure 12-11 Data Sampling for Noise Detection
183
Figure 12-12 Tx/Rx Swap
183
Table 12-4 Maximum Allowable Deviation
183
Interrupts
184
I/O Pin Control
184
USART Registers
184
Figure 12-13 USART Interrupt Map Diagram
184
Table 12-5 USART Interrupt Requests
184
Table 12-6 USART Register Map and Reset Value
184
Status Register (USART_STS)
185
Data Register (USART_DT)
186
Baud Rate Register (USART_BAUDR)
186
Control Register 1 (USART_CTRL1)
187
Control Register 2 (USART_CTRL2)
189
Control Register 3 (USART_CTRL3)
190
Guard Time and Divider Register (GDIV)
192
Receiver Timeout Detection Register (RTOV)
192
Interrupt Flag Clear Register (IFC)
192
Serial Peripheral Interface (SPI)
193
SPI Introduction
193
Functional Overview
193
SPI Overview
193
Figure 13-1 SPI Block Diagram
193
Full-Duplex/Half-Duplex Mode Selector
194
Figure 13-2 SPI Two-Wire Unidirectional Full-Duplex Connection
194
Figure 13-3 Single-Wire Unidirectional Receive Only in SPI Master Mode
195
Figure 13-4 Single-Wire Unidirectional Receive Only in SPI Slave Mode
195
Figure 13-5 Single-Wire Bidirectional Half-Duplex Mode
195
Chip Select Controller
196
SPI_SCK Controller
196
CRC Overview
197
DMA Transfer
198
TI Mode Overview
198
Transmitter
199
Receiver
199
Motorola Mode
200
Figure 13-6 Master Full-Duplex Communications
200
Figure 13-7 Slave Full-Duplex Communications
201
Figure 13-8 Master Half-Duplex Transmit
201
Figure 13-9 Slave Half-Duplex Receive
201
TI Mode Communication Timings
202
Figure 13-10 Slave Half-Duplex Transmit
202
Figure 13-11 Master Half-Duplex Receive
202
Figure 13-12 TI Mode Continous Transfer
202
Interrupts
203
IO Pin Control
203
Figure 13-13 TI Mode Continous Transfer with Dummy CLK
203
Figure 13-14 TI Mode Continous Transfer with Dummy CLK
203
Figure 13-15 SPI Interrupts
203
I 2 S Functional Description
204
I S Introduction
204
Figure 13-16 I 2 S Block Diagram
204
S Full-Duplex Mode
205
Operating Mode Selection
205
Figure 13-17 I 2 S Full-Duplex Structure
205
Figure 13-18 I 2 S Slave Device Transmission
206
Figure 13-19 I 2 S Slave Device Reception
206
Figure 13-20 I 2 S Master Device Transmission
206
Audio Protocol Selector
207
Figure 13-21 I S Master Device Reception
207
I2S_CLK Controller
208
Figure 13-22 CK & MCK Source in Master Mode
208
DMA Transfer
209
Table 13-1 Audio Frequency Precision Using System Clock
209
Transmitter/Receiver
210
I2S Communication Timings
211
Interrupts
211
IO Pin Control
211
Figure 13-23 Audio Standard Timings
211
Figure 13-24 I 2 S Interrupts
211
SPI Registers
212
SPI Control Register1 (SPI_CTRL1)
212
Mode)
212
Table 13-2 SPI Register Map and Reset Value
212
SPI Control Register2 (SPI_CTRL2)
213
SPI Status Register (SPI_STS)
214
SPI Data Register (SPI_DT)
215
SPICRC Register (SPI_CPOLY)
215
Mode)
215
Spirxcrc Register (SPI_RCRC)
215
Spitxcrc Register (SPI_TCRC)
215
SPI_I2S Register (SPI_I2SCTRL)
215
SPI_I2S Prescaler Register (SPI_I2SCLKP)
216
Full-Duplexed I2S (I2SF)
217
I2SF Introduction
217
I2SF Functional Overview
217
I2SF Full Duplex Mode
217
Figure 14-1 I2SF Full-Duplex Host Transmit/Slave Transmit
217
Figure 14-2 I2SF Full-Duplex Host Transmit/Slave Receive
217
I2SF Master Clock Sources
218
Figure 14-3 I2SF Full-Duplex Host Receive/Slave Transmit
218
Figure 14-4 I2SF Full-Duplex Host Receive/Slave Receive
218
PCM Mode
219
Figure 14-5 I2SF Master Clock Sources
219
Figure 14-6 Data Sampling on Falling Edge in PCM Mode
219
Figure 14-7 Data Sampling on Rising Edge in PCM Mode
219
Interrupts
220
IO Pin Control
220
Special Notes on I2SF
220
Figure 14-8 I2SF Interrupts
220
I2SF Registers
221
I2SF Control Register 2 (I2SF_CTRL2)
221
I2SF Status Register (I2SF_STS)
221
Table 14-1 I2SF5 Register Map and Reset Value
221
I2SF Data Register (I2SF_DT)
222
I2SF Register (I2SF_I2SCTRL)
222
I2SF Prescaler Register (I2SF_I2SCLKP)
223
I2SF Additional Register (I2SF_MISC1)
223
Timer
224
Table 15-1 TMR Functional Comparison
224
Basic Timer (TMR6 and TMR7)
225
TMR6 and TMR7 Introduction
225
TMR6 and TMR7 Main Features
225
TMR6 and TMR7 Function Overview
225
Counting Clock
225
Counting Mode
225
Figure 15-1 Basic Timer Block Diagram
225
Figure 15-2 Control Circuit with CK_INT Divided by 1
225
Figure 15-3 Basic Structure of a Counter
226
Figure 15-4 Overflow Event When PRBEN=0
226
Figure 15-5 Overflow Event When PRBEN=1
226
Figure 15-6 Counting Timing Diagram When the Prescaler Division Is 4
226
Debug Mode
227
TMR6 and TMR7 Registers
227
TMR6 and TMR7 Control Register1 (Tmrx_Ctrl1)
227
Table 15-2 TMR6 and TMR7 Register Table and Reset Value
227
TMR6 and TMR7 Control Register2 (Tmrx_Ctrl2)
228
TMR6 and TMR7 Dma/Interrupt Enable Register (Tmrx_Iden)
228
TMR6 and TMR7 Interrupt Status Register (Tmrx_Ists)
228
TMR6 and TMR7 Software Event Register (Tmrx_Sw EVT)
228
TMR6 and TMR7 Counter Value (Tmrx_Cval)
228
TMR6 and TMR7 Division (Tmrx_Div)
228
TMR6 and TMR7 Period Register (Tmrx_Pr)
229
General-Purpose Timer (TMR2 to TMR4)
229
TMR2 to TMR4 Introduction
229
TMR2 to TMR4 Main Features
229
TMR2 to TMR4 Functional Overview
229
Counting Clock
229
Figure 15-7 General-Purpose Timer Block Diagram
229
Figure 15-8 Counting Clock
230
Figure 15-9 Control Circuit with CK_INT, Tmrx_Div=0X0 and Tmrx_Pr=0X16
230
Figure 15-10 Block Diagram of External Clock Mode a
231
Figure 15-11 Counting in External Clock Mode A, Pr=0X32 and DIV=0X0
231
Figure 15-12 Block Diagram of External Clock Mode B
231
Figure 15-13 Counting in External Clock Mode B, Pr=0X32 and DIV=0X0
232
Figure 15-14 Counter Timing with Prescaler Value Chang from 1 to 4
232
Table 15-3 Tmrx Internal Trigger Connection
232
Counting Mode
233
Figure 15-15 Basic Structure of a Counter
233
Figure 15-16 Overflow Event When PRBEN=0
233
Figure 15-17 Overflow Event When PRBEN=1
234
Figure 15-18 Counter Timing Diagram with Internal Clock Divided by 4
234
Figure 15-19 Counter Timing Diagram with Internal Clock Divided by 1 and Tmrx_Pr=0X32
234
Figure 15-20 Encoder Mode Structure
235
TMR Input Function
236
Figure 15-21 Example of Counter Behavior in Encoder Interface Mode (Encoder Mode C)
236
Table 15-4 Counting Direction Versus Encoder Signals
236
Figure 15-22 Input/Output Channel 1 Main Circuit
237
Figure 15-23 Channel 1 Input Stage
237
TMR Output Function
238
Figure 15-24 PWM Input Mode Configuration Example
238
Figure 15-25 PWM Input Mode
238
Figure 15-26 Capture/Compare Channel Output Stage (Channel 1 to 4)
238
Figure 15-27 C1ORAW Toggles When Counter Value Matches the C1DT Value
240
Figure 15-28 Upcounting Mode and PWM Mode a
240
Figure 15-29 Up/Down Counting Mode and PWM Mode a
241
Figure 15-30 One-Pulse Mode
241
TMR Synchronization
242
Figure 15-31 Clearing Cxoraw(PWM Mode B) by EXT Input
242
Figure 15-32 Example of Reset Mode
242
Figure 15-33 Example of Suspend Mode
242
Figure 15-34 Example of Trigger Mode
243
Figure 15-35 Master/Slave Timer Connection
243
Debug Mode
244
TMR2 to TMR4 Registers
244
Figure 15-36 Using Master Timer to Start Slave Timer
244
Figure 15-37 Starting Master and Slave Timers Synchronously by an External Trigger
244
Control Register 1 (Tmrx_Ctrl1)
245
Table 15-5 TMR2 to TMR4 Register Map and Reset Value
245
Control Register 2 (Tmrx_Ctrl2)
246
Slave Timer Control Register (Tmrx_Stctrl)
246
Dma/Interrupt Enable Register (Tmrx_Iden)
247
Interrupt Status Register (Tmrx_Ists)
248
Software Event Register (Tmrx_Swevt)
249
Channel Mode Register1 (Tmrx_Cm1)
249
Channel Mode Register2 (Tmrx_Cm2)
251
Channel Control Register (Tmrx_Cctrl)
252
Counter Value (Tmrx_Cval)
253
Frequency Division Value (Tmrx_Div)
253
Period Register (Tmrx_Pr)
253
Channel 1 Data Register (Tmrx_C1Dt)
253
Table 15-6 Standard Cxout Channel Output Control Bit
253
Channel 2 Data Register (Tmrx_C2Dt)
254
Channel 3 Data Register (Tmrx_C3Dt)
254
Channel 4 Data Register (Tmrx_C4Dt)
254
DMA Control Register (Tmrx_Dmactrl)
254
DMA Data Register (Tmrx_Dmadt)
255
TMR2 Channel Input Remap Register (TMR2_RMP)
255
General-Purpose Timer (TMR9)
255
TMR9 Introduction
255
TMR9 Main Features
255
TMR9 Functional Overview
256
Counting Clock
256
Figure 15-38 Block Diagram of General-Purpose TMR9
256
Figure 15-39 Counting Clock
256
Figure 15-40 Control Circuit with CK_INT, Tmrx_Div=0X0 and Tmrx_Pr=0X16
257
Figure 15-41 Block Diagram of External Clock Mode a
257
Figure 15-42 Counting in External Clock Mode A, Pr=0X32 and DIV=0X0
258
Table 15-7 Tmrx Internal Trigger Connection
258
Counting Mode
259
Figure 15-43 Counter Timing with Prescaler Value Chang from 1 to 4
259
Figure 15-44 Basic Structure of a Counter
259
Figure 15-45 Overflow Event When PRBEN=0
260
Figure 15-46 Overflow Event When PRBEN=1
260
Figure 15-47 Counter Timing Diagram with Internal Clock Divided by 4
260
Figure 15-48 Counter Timing Diagram with Internal Clock Divided by 1 and Tmrx_Pr=0X32
261
Figure 15-49 OVFIF in Upcounting Mode and Central-Aligned Mode
261
Figure 15-50 Encoder Mode Structure
262
TMR Input Function
263
Figure 15-51 Example of Counter Behavior in Encoder Interface Mode (Encoder Mode C)
263
Table 15-8 Counting Direction Versus Encoder Signals
263
Figure 15-52 Input/Output Channel 1 Main Circuit
264
Figure 15-53 Channel 1 Input Stage
264
Figure 15-54 PWM Input Mode Configuration Example
265
Figure 15-55 PWM Input Mode
265
TMR Output Function
266
Figure 15-56 Channel 1 Output Stage
266
Figure 15-57 Channel 2 Output Stage
266
Figure 15-58 C1ORAW Toggles When Counter Value Matches the C1DT Value
267
Figure 15-59 Upcounting Mode and PWM Mode a
267
Figure 15-60 One-Pulse Mode
268
Figure 15-61 Complementary Output with Dead-Time Insertion
268
TMR Break Function
269
Figure 15-62 TMR Output Control
269
TMR Synchronization
270
Figure 15-63 Example of TMR Break Function
270
Figure 15-64 Example of Reset Mode
270
Debug Mode
271
TMR9 Registers
271
Figure 15-65 Example of Suspend Mode
271
Figure 15-66 Example of Trigger Mode
271
Table 15-9 TMR9 Register Map and Reset Value
271
TMR9 Control Register1 (Tmrx_Ctrl1)
272
TMR9 Control Register 2 (Tmrx_Ctrl2)
273
TMR9 Slave Timer Control Register (Tmrx_Stctrl)
273
TMR9 Dma/Interrupt Enable Register (Tmrx_Iden)
274
TMR9 Interrupt Status Register (Tmrx_Ists)
274
TMR9 Software Event Register (Tmrx_Swevt)
275
TMR9 Channel Mode Register 1 (Tmrx_Cm1)
276
TMR9 Channel Control Register (Tmrx_Cctrl)
278
Table 15-10 Complementary Output Channel Cxout and Cxcout Control Bits with Break Function
279
TMR9 Counter Value (Tmrx_Cval)
280
TMR9 Division Value (Tmrx_Div)
280
TMR9 Period Register (Tmrx_Pr)
280
TMR9 Repetition Period Register (Tmrx_Rpr)
280
TMR9 Channel 1 Data Register (Tmrx_C1Dt)
280
TMR9 Channel 2 Data Register (Tmrx_C2Dt)
280
TMR9 Break Register (Tmrx_Brk)
280
TMR9 DMA Control Register (Tmrx_Dmactrl)
282
TMR9 DMA Data Register (Tmrx_Dmadt)
282
General-Purpose Timer (TMR10/11/13/14)
283
Tmrx Introduction
283
Tmrx Main Features
283
Tmrx Functional Overview
283
Counting Clock
283
Figure 15-67 TMR10/11/13/14 Block Diagram
283
Figure 15-68 Basic Structure of a Counter
283
Counting Mode
284
Figure 15-69 Control Circuit with CK_INT, Tmrx_Div=0X0 and Pr=0X16
284
Figure 15-70 Basic Structure of a Counter
284
Figure 15-71 Overflow Event When PRBEN=0
285
Figure 15-72 Overflow Event When PRBEN=1
285
Figure 15-73 Counter Timing Diagram with Internal Clock Divided by 4
285
Figure 15-74 Counter Timing Diagram with Internal Clock Divided by 1 and Tmrx_Pr=0X32
286
TMR Input Function
287
Figure 15-75 OVFIF in Upcounting Mode and Central-Aligned Mode
287
TMR Output Function
288
Figure 15-76 Input/Output Channel 1 Main Circuit
288
Figure 15-77 Channel 1 Input Stage
288
Figure 15-78 Channel 1 Output Stage
288
Figure 15-79 C1ORAW Toggles When Counter Value Matches the C1DT Value
290
Figure 15-80 Upcounting Mode and PWM Mode a
290
Figure 15-81 One-Pulse Mode
290
TMR Break Function
291
Figure 15-82 Complementary Output with Dead-Time Insertion
291
Debug Mode
292
Figure 15-83 TMR Output Control
292
Figure 15-84 Example of TMR Break Function
292
Tmrx Registers
293
Tmrx Control Register1 (Tmrx_Ctrl1) (X=10/11/13/14)
293
Table 15-11 TMR10/11/13/14 Register Map and Reset Value
293
Tmrx Control Register 2 (Tmrx_Ctrl2) (X=10/11/13/14)
294
Tmrx Dma/Interrupt Enable Register (Tmrx_Iden
294
Tmrx Interrupt Status Register (Tmrx_Ists) (X=10/11/13/14)
295
Tmrx Software Event Register (Tmrx_Swevt) (X=10/11/13/14)
295
Tmrx Channel Mode Register1 (Tmrx_Cm1) (X=10/11/13/14)
296
Tmrx Channel Control Register (Tmrx_Cctrl) (X=10/11/13/14)
297
Table 15-12 Complementary Output Channel Cxout and Cxcout Control Bits with Break Function
299
Tmrx Counter Value (Tmrx_Cval) (X=10/11/13/14)
300
Tmrx Division Value (Tmrx_Div) (X=10/11/13/14)
300
Tmrx Period Register (Tmrx_Pr) (X=10/11/13/14)
300
Tmrx Repetition Period Register (Tmrx_Rpr) (X=10/11/13/14)
300
Tmrx Channel 1 Data Register (Tmrx_C1Dt) (X=10/11/13/14)
300
Tmrx Break Register (Tmrx_Brk) (X=10/11/13/14)
300
TMRX DMA Control Register (TMRX_DMACTRL) (X=10/11/13/14)
302
Tmrx DMA Data Register (Tmrx_Dmadt) (X=10/11/13/14)
302
TMR14 Channel Input Remap Register (Tmrx_Rmp)
302
Advanced-Control Timers (TMR1)
303
TMR1 Introduction
303
TMR1 Main Features
303
TMR1 Functional Overview
303
Counting Clock
303
Figure 15-85 Block Diagram of Advanced-Control Timer
303
Figure 15-86 Counting Clock
304
Figure 15-87 Control Circuit with CK_INT, Tmrx_Div=0X0 and Tmrx_Pr=0X16
304
Figure 15-88 Block Diagram of External Clock Mode a
305
Figure 15-89 Counting in External Clock Mode A, Pr=0X32 and DIV=0X0
305
Figure 15-90 Block Diagram of External Clock Mode B
305
Counting Mode
306
Figure 15-91 Counting in External Clock Mode B, Pr=0X32 and DIV=0X0
306
Figure 15-92 Counter Timing with Prescaler Value Changing from 1 to 4
306
Table 15-13 Tmrx Internal Trigger Connection
306
Figure 15-93 Basic Structure of a Counter
307
Figure 15-94 Overflow Event When PRBEN=0
307
Figure 15-95 Overflow Event When PRBEN=1
307
Figure 15-96 Counter Timing Diagram with Internal Clock Divided by 4
308
Figure 15-97 Counter Timing Diagram with Internal Clock Divided by 1 and Tmrx_Pr=0X32
308
Figure 15-98 OVFIF Behavior in Upcounting Mode and Center-Aligned Mode
309
Figure 15-99 Structure of Encoder Mode
309
Figure 15-100 Example of Encoder Interface Mode C
310
Table 15-14 Counting Direction Versus Encoder Signals
310
TMR Input Function
311
Figure 15-101 Input/Output Channel 1 Main Circuit
311
Figure 15-102 Channel 1 Input Stage
311
Figure 15-103 PWM Input Mode Configuration Example
312
TMR Output Function
313
Figure 15-104 PWM Input Mode
313
Figure 15-105 Channel Output Stage (Channel 1 to 3)
313
Figure 15-106 Channel 4 Output Stage
313
Figure 15-107 C1ORAW Toggles When Counter Value Matches the C1DT Value
315
Figure 15-108 Upcounting Mode and PWM Mode a
315
Figure 15-109 Up/Down Counting Mode and PWM Mode
315
Figure 15-110 One-Pulse Mode
316
Figure 15-111 Clearing Cxoraw (PWM Mode A) by EXT Input
316
TMR Break Function
317
Figure 15-112 Complementary Output with Dead-Time Insertion
317
TMR Synchronization
318
Figure 15-113 TMR Output Control
318
Figure 15-114 Example of TMR Break Function
318
Figure 15-115 Example of Reset Mode
319
Figure 15-116 Example of Suspend Mode
319
Figure 15-117 Example of Trigger Mode
319
Debug Mode
320
TMR1 Registers
320
TMR1 Control Register1 (TMR1_CTRL1)
320
Table 15-15 TMR1 Register Map and Reset Value
320
TMR1 Control Register2 (TMR1_CTRL2)
321
TMR1 Slave Timer Control Register (TMR1_STCTRL)
322
TMR1 Dma/Interrupt Enable Register (TMR1_IDEN)
323
TMR1 Interrupt Status Register (TMR1_ISTS)
324
TMR1 Software Event Register (TMR1_SWEVT)
325
TMR1 Channel Mode Register1 (TMR1_CM1)
325
TMR1 Channel Mode Register2 (TMR1_CM2)
327
TMR1 Channel Control Register (TMR1_CCTRL)
328
Table 15-16 Complementary Output Channel Cxout and Cxcout Control Bits with Break Function
329
TMR1 Counter Value (TMR1_CVAL)
330
TMR1 Division Value (TMR1_DIV)
330
TMR1 Period Register (TMR1_PR)
330
TMR1 Repetition Period Register (TMR1_RPR)
330
TMR1 Channel 1 Data Register (TMR1_C1DT)
330
TMR1 Channel 2 Data Register (TMR1_C2DT)
331
TMR1 Channel 3 Data Register (TMR1_C3DT)
331
TMR1 Channel 4 Data Register (Tmrx_C4Dt)
331
TMR1 Break Register (TMR1_BRK)
331
TMR1 DMA Control Register (TMR1_DMACTRL)
332
TMR1 DMA Data Register (TMR1_DMADT)
333
TMR1 Channel Mode Register3 (TMR1_ CM3)
333
TMR1 Channel 5 Data Register (TMR1_C5DT)
333
Window Watchdog Timer (WWDT)
334
WWDT Introduction
334
WWDT Main Features
334
WWDT Functional Overview
334
Figure 16-1 Window Watchdog Block Diagram
334
Debug Mode
335
WWDT Registers
335
Control Register (WWDT_CTRL)
335
Figure 16-2 Window Watchdog Timing Diagram
335
Table 16-1 Minimum and Maximum Timeout Value When PCLK1=72 Mhz
335
Table 16-2 WWDT Register Map and Reset Value
335
Configuration Register (WWDT_CFG)
336
Status Register (WWDT_STS)
336
Watchdog Timer (WDT)
337
WDT Introduction
337
WDT Main Features
337
WDT Functional Overview
337
Debug Mode
338
WDT Registers
338
Figure 17-1 WDT Block Diagram
338
Table 17-1 WDT Timeout Period (Lick=40Khz)
338
Table 17-2 WDT Register and Reset Value
338
Command Register (WDT_CMD)
339
Divider Register (WDT_DIV)
339
Reload Register (WDT_RLD)
339
Status Register (WDT_STS)
339
Window Register (WDT_WIN)
340
Enhanced Real-Time Clock (ERTC)
341
ERTC Introduction
341
ERTC Main Features
341
Figure 18-1 ERTC Block Diagram
341
ERTC Function Overview
342
ERTC Clock
342
ERTC Initialization
342
Table 18-1 RTC Register Map and Reset Values
342
Periodic Automatic Wakeup
344
ERTC Calibration
344
Reference Clock Detection
345
Time Stamp Function
345
Tamper Detection
346
Multiplexed Function Output
346
ERTC Wakeup
347
Table 18-2 ERTC Low-Power Mode Wakeup
347
Table 18-3 Interrupt Control Bits
347
ERTC Registers
348
ERTC Time Register (ERTC_TIME)
348
Table 18-4 ERTC Register Map and Reset Values
348
ERTC Date Register (ERTC_DATE)
349
ERTC Control Register (ERTC_CTRL)
349
ERTC Initialization and Status Register (ERTC_STS)
350
ERTC Divider Register (ERTC_DIV)
352
ERTC Wakeup Timer Register (ERTC_WAT)
352
ERTC Alarm Clock a Register (ERTC_ALA)
352
ERTC Alarm Clock B Register (ERTC_ALB)
352
ERTC Write Protection Register (ERTC_WP)
353
ERTC Subsecond Register (ERTC_SBS)
353
ERTC Time Adjustment Register (ERTC_TADJ)
353
ERTC Time Stamp Time Register (ERTC_TSTM)
353
ERTC Time Stamp Date Register (ERTC_TSDT)
354
ERTC Time Stamp Subsecond Register (ERTC_TSSBS)
354
ERTC Smooth Calibration Register (ERTC_SCAL)
354
ERTC Tamper Configuration Register (ERTC_TAMP)
355
ERTC Alarm Clock a Subsecond Register (ERTC_ALASBS)
356
ERTC Alarm Clock B Subsecond Register (ERTC_ALBSBS)
356
ERTC Battery Powered Domain Data Register (Ertc_Bprx)
356
Analog-To-Digital Converter (ADC)
357
ADC Introduction
357
ADC Main Features
357
ADC Structure
358
Figure 19-1 ADC Block Diagram
358
ADC Functional Overview
359
Channel Management
359
Internal Temperature Sensor
359
Internal Reference Voltage
359
ADC Operation Process
359
Power-On and Calibration
360
Figure 19-2 ADC Basic Operation Process
360
Trigger
361
Sampling and Conversion Sequence
361
Figure 19-3 ADC Power-On and Calibration
361
Table 19-1 Trigger Sources for Ordinary Channels
361
Conversion Sequence Management
362
Sequence Mode
362
Preempted Group Automatic Conversion Mode
362
Figure 19-4 Sequence Mode
362
Figure 19-5 Preempted Group Auto Conversion Mode
362
Repetition Mode
363
Partition Mode
363
Figure 19-6 Repetition Mode
363
Figure 19-7 Partition Mode
363
Oversampling
364
Oversampling of Ordinary Group of Channels
364
Table 19-2 Correlation between Maximum Cumulative Data, Oversampling Multiple and Shift Digits
364
Oversampling of Preempted Group of Channels
365
Figure 19-8 Rdinary Oversampling Restart Mode Selection
365
Figure 19-9 Ordinary Oversampling Trigger Mode
365
Data Management
366
Data Alignment
366
Data Read
366
Voltage Monitoring
366
Figure 19-10 Oversampling of Preempted Group of Channels
366
Figure 19-11 Data Alignment
366
Status Flag and Interrupts
367
ADC Registers
367
Table 19-3 ADC Register Map and Reset Values
367
ADC Status Register (ADC_STS)
368
ADC Control Register1 (ADC_CTRL1)
368
ADC Control Register2 (ADC_CTRL2)
370
ADC Sampling Time Register 1 (ADC_SPT1)
371
ADC Sampling Time Register 2 (ADC_SPT2)
372
ADC Preempted Channel Data Offset Register X (ADC_ Pcdtox) (X=1
375
ADC Voltage Monitoring High Threshold Register (ADC_VWHB)
375
ADC Voltage Monitor Low Threshold Register (ADC_ VWLB)
375
ADC Ordinary Sequence Register 1 (ADC_ OSQ1)
375
ADC Ordinary Sequence Register 2 (ADC_ OSQ2)
375
ADC Ordinary Sequence Register 3 (ADC_ OSQ3)
376
ADC Preempted Sequence Register (ADC_PSQ)
376
ADC Preempted Data Register X (ADC_ Pdtx) (X=1
376
ADC Ordinary Data Register (ADC_ ODT)
376
ADC Oversampling Register (ADC_OVSP)
377
ADC Common Control Register (ADC_CCTRL)
377
Controller Area Network (CAN)
378
CAN Introduction
378
CAN Main Features
378
Baud Rate
378
Figure 20-1 Bit Timing
378
Figure 20-2 Frame Type
380
Interrupt Management
381
Figure 20-3 Transmit Interrupt Generation
381
Figure 20-4 Receive Interrupt 0 Generation
381
Figure 20-5 Receive Interrupt 1 Generation
381
Figure 20-6 Status Error Interrupt Generation
381
Design Tips
382
Functional Overview
382
General Description
382
Figure 20-7 CAN Block Diagram
382
Operating Modes
383
Test Modes
384
Message Filtering
384
Figure 20-8 32-Bit Identifier Mask Mode
384
Figure 20-9 32-Bit Identifier List Mode
385
Figure 20-10 16-Bit Identifier Mask Mode
385

ARTERY AT32F405 Series Getting Started (27 pages)

Brand: ARTERY | Category: Computer Hardware | Size: 2 MB

Table of Contents
2
List of Tables
3
Environment Requirements
6
Set up AT32 MCU Development Environment
6
Debugging Tool and Evaluation Board
6
Figure 1. AT-START-F405 Evaluation Board with AT-Link-EZ
6
Figure 2. AT-START-F405 Evaluation Board Package
6
Programming Tools and Software
7
AT32 MCU-Based Development Environment
7
Figure 3. ICP/ISP/AT-Link-Family
7
Figure 4. BSP Package at Artery's Official Website
7
Figure 5. Keil_V5 Templates
8
Figure 6. Pack Download
9
Figure 7. Set up Arterytek.at32F402_405 _DFP
9
Figure 8. Set up Keil4_At32Mcu_Addon
9
Figure 9. Pack Installer Icon in Keil
10
Figure 10. Set up Iar_At32Mcu_Addon
10
Figure 11. Keil Debug Option
10
Figure 12. Keil Debug Settings
11
Figure 13. Keil Utilities
11
Figure 14. IAR Debug Option
11
How to Quickly Replace AT32F415 with AT32F402
12
AT32F405 MCU Function Enhancement
12
Instruction Prefetch Buffer
12
Figure 15. IAR CMSIS-DAP Option
12
PLL Clock Configuration
13
Figure 16. Wait States in the FLASH_PSR Register
13
Figure 17. System_Clock_Config
13
Figure 18. Configure 216Mhz Output for AT32F405
13
Encryption Operation
14
Figure 19. PLL Auto Step Mode
14
Figure 20. Enable/Disable Access Protection with ISP
15
Figure 21. Enable Access Protection with ISP
15
Figure 22. Disable Access Protection with ISP
16
Figure 23. Enable Erase and Program Protection with ICP
17
Figure 24. Disable Erase and Program Protection with ICP
17
How to Set System Memory as Memory Extension
18
Figure 25. Select Boot Memory AP Mode with ICP
18
Figure 26. Confirm Whether Boot Memory AP Mode Is Successful
18
Figure 27. Confirm Whether Boot Memory AP Mode Is Successful in ICP
19
Figure 28. Configure Boot Memory AP Mode Offline with ICP
20
Figure 29. Project File Settings Offline in ICP
20
Distinguish AT32 MCU from Other MCUS
21
Figure 30. AT-Link Offline Download Status Monitoring with ICP
21
Figure 31. Read Cortex ID
21
Figure 32. Read PID and UID
21
Frequently Asked Questions
22
Enter Hard Fault Handler
22
J-Link Fails to Identify IC in Keil
22
Problems Occurred in Program Download
22

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ARTERY AT32F405 Series Reference Manual (516 pages)

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ARTERY AT32F405 Series Getting Started (27 pages)

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