Memory Map; Outlines - Toshiba TXZ+ TMPM4MNFYAFG Reference Manual

32-bit risc microcontroller, clock control and operation mode

Table of Contents

2. Memory map

The memory maps for TMPM4M Group(1) are based on the Arm Cortex-M4(with FPU) processor core memory

map.

The internal ROM, internal RAM and special function registers (SFR) of TMPM4M Group(1) are mapped to the

Code, SRAM and peripheral regions of the Cortex-M4(with FPU) respectively. The special function register

(SFR) means the control registers of all input/output ports and peripheral functions.

The CPU register region is the processor core's internal register region.

For more information on each region, see the "Arm documentation set for the Arm Cortex-M4".

Note that access to regions indicated as "Fault" causes a bus fault if bus faults are enabled, or causes a hard fault if

bus faults are disabled. Also, do not access the vendor-specific region.

Clock Control and Operation Mode

43 / 64

TXZ+ Family

TMPM4M Group(1)

2022-06-24

Rev. 1.1

Table of Contents

Cg-m4m(1)-e