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Architecture
2.2
Signal Descriptions
The VLYNQ module on the DM646x device is configurable for a 1 to 4 bit-wide RX/TX.
If the configured width does not match the number of transmit/receive lines that are available on the
remote device, negotiation between the two VLYNQ devices automatically configures the width (see
Section
2.6).
The VLYNQ interface signals are shown in
Pin Name
Signal Name
VLYNQ_CLOCK
VLYNQ serial clock
VLYNQ_SCRUN
VLYNQ serial clock
run request
(Active low)
VLYNQ_RXD[0:3] VLYNQ receive data
VLYNQ_TXD[0:3] VLYNQ transmit data
2.3
Protocol Description
VLYNQ relies on 8b/10b block coding to minimize the number of serial pins and allows for in-band packet
delineation and control.
Appendix A
provides general information on 8b/10b coding definitions and their implementation within the
VLYNQ module in the DM646x device.
12
VLYNQ Port
Table
1.
Table 1. VLYNQ Port Pins
I/O
Description
I/O
The VLYNQ reference clock supports the internally or externally generated
clock.
I/O
The VLYNQ serial clock run request allows remote requests for the VLYNQ
serial clock to be turned off for system power management.
Low: The request VLYNQ serial clock is active.
High: The VLYNQ serial clock is requested to be high when all transactions are
complete.
I
VLYNQ receive data is synchronous with the VLYNQ serial clock.
O
VLYNQ transmit data is synchronous with the VLYNQ serial clock.
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SPRUER8 – December 2007
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