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Related Manuals for Texas Instruments TMS320DM646 Series
Summary of Contents for Texas Instruments TMS320DM646 Series
- Page 1 TMS320DM646x DMSoC VLYNQ Port User's Guide Literature Number: SPRUER8 December 2007...
- Page 2 SPRUER8 – December 2007 Submit Documentation Feedback...
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Page 3: Table Of Contents
Contents ..........................Preface ........................ Introduction ..................Purpose of the Peripheral ......................Features ..................Functional Block Diagram ............... Industry Standard(s) Compliance Statement ......................Architecture ....................Clock Control ..................... Signal Descriptions .................... Protocol Description ................VLYNQ Functional Description ...................... Initialization ....................Auto Negotiation .................... - Page 4 ..................VLYNQ 2.0 Packet Format .................... VLYNQ 2.X Packets .................. Appendix B Write/Read Performance ....................Write Performance ..................... Read Performance Contents SPRUER8 – December 2007 Submit Documentation Feedback...
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Page 5: List Of Figures
List of Figures ................. VLYNQ Port Functional Block Diagram .................... External Clock Block Diagram ..................... Internal Clock Block Diagram ....................VLYNQ Module Structure ......................Write Operations ......................Read Operations ..................Example Address Memory Map ............... Interrupt Generation Mechanism Block Diagram .................... - Page 6 List of Tables ......................VLYNQ Port Pins .............. Address Translation Example (Single Mapped Region) .............. Address Translation Example (Single Mapped Region) ......................VLYNQ Interrupt ..................VLYNQ Register Address Space ..................VLYNQ Port Controller Registers ................. Revision Register (REVID) Field Descriptions ................
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Page 7: Preface
SPRAA84 — TMS320C64x to TMS320C64x+ CPU Migration Guide. Describes migrating from the Texas Instruments TMS320C64x digital signal processor (DSP) to the TMS320C64x+ DSP. The objective of this document is to indicate differences between the two cores. Functionality in the devices that is identical is not included. - Page 8 Related Documentation From Texas Instruments Trademarks VLYNQ is a trademark of Texas Instruments. Read This First SPRUER8 – December 2007 Submit Documentation Feedback...
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Page 9: Introduction
User's Guide SPRUER8 – December 2007 VLYNQ Port Introduction Purpose of the Peripheral The VLYNQ™ communications interface port is a serial interface with a low pin count, high-speed point-to-point serial interface in the TMS320DM646x Digital Media System-on-Chip (DMSoC) for connecting to host processors and other VLYNQ compatible devices. The VLYNQ port is a full-duplex serial bus where transmit and receive operations occur separately and simultaneously without interference. -
Page 10: Functional Block Diagram
Off chip (remote) device access VLQINT INT38 ARM interrupt controller Industry Standard(s) Compliance Statement VLYNQ is an interface defined by Texas Instruments and does not conform to any other industry standard. VLYNQ Port SPRUER8 – December 2007 Submit Documentation Feedback... -
Page 11: Architecture
www.ti.com Architecture Architecture This section discusses the architecture and basic functions of the VLYNQ peripheral. Clock Control The VLYNQ internal system clock is derived from SYSCLK3, which is the PLL0 clock divided by 4. For detailed information on the PLLs and clock distribution on the processor, see the TMS320DM646x DMSoC ARM Subsystem Reference Guide (SPRUEP9). -
Page 12: Signal Descriptions
www.ti.com Architecture Signal Descriptions The VLYNQ module on the DM646x device is configurable for a 1 to 4 bit-wide RX/TX. If the configured width does not match the number of transmit/receive lines that are available on the remote device, negotiation between the two VLYNQ devices automatically configures the width (see Section 2.6). -
Page 13: Vlynq Functional Description
www.ti.com Architecture VLYNQ Functional Description The VLYNQ core supports both host-to-peripheral and peer-to-peer communication models and is symmetrical. The VLYNQ module structure is shown in Figure Figure 4. VLYNQ Module Structure System clock VLYNQ clock Outbound Slave Address Outbound 8B/10B Serial config bus command... -
Page 14: Write Operations
www.ti.com Architecture Figure 5. Write Operations System clock VLYNQ clock Serial Slave Outbound TxData Address Outbound 8B/10B config bus TxSM Serializer command translation commands encoding interface FIFO Return data FIFO Registers Local VLYNQ Return data FIFO Master Inbound Address Inbound 8B/10B Serial config bus... -
Page 15: Read Operations
www.ti.com Architecture Figure 6. Read Operations System clock VLYNQ Clock Serial Outbound Slave TxData Address Outbound 8B/10B config bus command TxSM Serializer translation commands encoding interface FIFO Return data FIFO Registers Local VLYNC Return data FIFO Serial Master Inbound RxData Address Inbound 8B/10B... -
Page 16: Initialization
www.ti.com Architecture Initialization Since VLYNQ devices can be controlled solely over the serial interface (that is, no local CPU exists), an automatic reliable initialization sequence (without user configuration) establishes a connection between two VLYNQ devices, just after a VLYNQ module is enabled and auto-negotiation occurs. Auto-negotiation is defined in Section 2.6. -
Page 17: Example Address Memory Map
www.ti.com Architecture At the remote device, the transmitted address is used to determine, which remote mapped region is being accessed. This is achieved by summing each memory size sequentially until the memory size is larger than the transmitted address. The last memory size added is the region targeted. The remote map is specified by a memory size and an offset, programmed in the RX Address Map Size (RAMSn) register and RX Address Map Offset (RAMOn) in the remote device. -
Page 18: Address Translation Example (Single Mapped Region)
www.ti.com Architecture DM646x VLYNQ Module: 4C00 0054h Initial address at the slave configuration bus subtract 4C00 0000h TX Address Map Register (no need to change the reset value for DM646x , for this register) 0000 0054h Translated address to remote device via serial interface Remote VLYNQ Module: 0000 0054h Initial address from the RX serial interface... -
Page 19: Flow Control
www.ti.com Architecture Example 1. Address Translation Example The remote address 0400 0154h (or 0000 0054h) was translated to 8200 0054h on the DM646x (local) device. The translated address for packets received on the serial interface is determined as follows: If (RX Packet Address < RX Address Map Size 1 Register) { Translated Address = RX Packet Address + RX Address Map Offset 1 Register } else if (RX Packet Address <... -
Page 20: Reset Considerations
www.ti.com Architecture Reset Considerations 2.9.1 Software Reset Considerations Peripheral clock and reset control is done through the power and sleep controller (PSC) module that is included with the device. For more information, refer to the power management section (Section 2.12). Additionally, there is a software reset (the reset bit in the VLYNQ control register, CTRL) within the peripheral itself. -
Page 21: Interrupt Generation Mechanism Block Diagram
www.ti.com Architecture When INTLOCAL = 0, the contents of INTPENDSET are inserted into an interrupt packet and sent over the serial interface. When packet transmission completes, the associated bits clear in INTPENDSET. When INTLOCAL = 1, bits in INTPENDSET transfer to the VLYNQ interrupt status/clear register (INTSTATCLR). - Page 22 www.ti.com Architecture 2.10.3 Remote Interrupts Remote interrupts occur when an interrupt packet is received over the serial interface from a remote device. The interrupt status is extracted from the packet and written to a location pointed to by the interrupt pointer register (INTPTR). The INTPTR should contain the address of the interrupt pending/set register (INTPENDSET).
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Page 23: 2.11 Dma Event Support
www.ti.com Architecture 2.11 DMA Event Support The VLYNQ module on the DM646x device is classified as a master peripheral. Classification as a master peripheral normally implies that the peripheral is able to sustain its own transfers without relying on any external peripherals (for example, the system DMA, etc). -
Page 24: 2.13 Emulation Considerations
www.ti.com Registers 2.13 Emulation Considerations During debug, the ARM CPU may be halted for single stepping, bench marking, profiling, or other debug uses using the emulator. VLYNQ does not support emulation halts/suspend operation. VLYNQ operations continue during emulation halt/suspend. 2.14 Programming Guide The sequence below sets up the local VLYNQ to function in basic mode. -
Page 25: Revision Register (Revid)
www.ti.com Registers Table 6. VLYNQ Port Controller Registers Offset Acronym Register Description Section REVID Revision Register Section 3.1 CTRL Control Register Section 3.2 STAT Status Register Section 3.3 INTPRI Interrupt Priority Vector Status/Clear Register Section 3.4 INTSTATCLR Interrupt Status/Clear Register Section 3.5 INTPENDSET Interrupt Pending/Set Register... -
Page 26: Control Register (Ctrl)
www.ti.com Registers Control Register (CTRL) The control register (CTRL) determines operation of the VLYNQ module. The CTRL is shown in Figure 10 and described in Table Figure 10. Control Register (CTRL) PMEN SCLKPUDIS Reserved RXSAMPELVAL RTMVALIDWR RTMENABLE TXFASTPATH Reserved CLKDIV R/W-0 R/W-0 R/W-3h... - Page 27 www.ti.com Registers Table 8. Control Register (CTRL) Field Descriptions (continued) Field Value Description INT2CFG Interrupt to configuration register. Determines which register is written with the status contained in interrupt packets that are received over the serial interface. Always write 1 to this bit and configure the interrupt pointer register to point to the interrupt pending/set register.
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Page 28: Status Register (Stat)
www.ti.com Registers Status Register (STAT) The status register (STAT) is used to detect conditions that may be of interest to the system designer. The STAT is shown in Figure 11 and described in Table Figure 11. Status Register (STAT) Reserved SWIDTHIN SWIDTHOUT Reserved... - Page 29 www.ti.com Registers Table 9. Status Register (STAT) Field Descriptions (continued) Field Value Description RERROR Remote Error. Write a 1 to this bit to clear it. No error This bit indicates that a downstream VLYNQ module has detected a packet error. This bit is set when an error indication, /E/, is received from the serial interface.
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Page 30: Interrupt Priority Vector Status/Clear Register (Intpri)
www.ti.com Registers Interrupt Priority Vector Status/Clear Register (INTPRI) The interrupt priority vector status/clear register (INTPRI) displays the highest priority vector with a pending interrupt when read. When writing, only bits [4:0] are valid, and the value represents the vector of the interrupt to be cleared. -
Page 31: Interrupt Pending/Set Register (Intpendset)
www.ti.com Registers Interrupt Pending/Set Register (INTPENDSET) The interrupt pending/set register (INTPENDSET) indicates the pending interrupt status when the INTLOCAL bit in the control register (CTRL) is not set. When the interrupt packet is forwarded on the serial interface, these bits are cleared. The INTPENDSET is shown in Figure 14 and described in Table... -
Page 32: Transmit Address Map Register (Xam)
www.ti.com Registers Transmit Address Map Register (XAM) The transmit address map register (XAM) is used to translate transmit packet addresses to remote device configuration bus addresses. The XAM is shown in Figure 16 and described in Table Figure 16. Transmit Address Map Register (XAM) TXADRMAP Reserved R/W-0... -
Page 33: Receive Address Map Size 1 Register (Rams1)
www.ti.com Registers Receive Address Map Size 1 Register (RAMS1) The receive address map size 1 register (RAMS1) is used to identify the intended destination of inbound serial packets. The RAMS1 is shown in Figure 17 and described in Table Figure 17. Receive Address Map Size 1 Register (RAMS1) RXADRSIZE1 Reserved R/W-0... -
Page 34: Receive Address Map Size 2 Register (Rams2)
www.ti.com Registers 3.11 Receive Address Map Size 2 Register (RAMS2) The receive address map size 2 register (RAMS2) is used to identify the intended destination of inbound serial packets. The RAMS2 is shown in Figure 19 and described in Table Figure 19. -
Page 35: Receive Address Map Size 3 Register (Rams3)
www.ti.com Registers 3.13 Receive Address Map Size 3 Register (RAMS3) The receive address map size 3 register (RAMS3) is used to identify the intended destination of inbound serial packets. The RAMS3 is shown in Figure 21 and described in Table Figure 21. -
Page 36: Receive Address Map Size 4 Register (Rams4)
www.ti.com Registers 3.15 Receive Address Map Size 4 Register (RAMS4) The receive address map size 4 register (RAMS4) is used to identify the intended destination of inbound serial packets. The RAMS4 is shown in Figure 23 and described in Table Figure 23. -
Page 37: Chip Version Register (Chipver)
www.ti.com Registers 3.17 Chip Version Register (CHIPVER) Each chip that has a VLYNQ module on it has a unique device ID associated with it, which is software readable via the chip version register (CHIPVER). The CHIPVER is shown in Figure 25 and described in Table Figure 25. -
Page 38: Remote Configuration Registers
www.ti.com Remote Configuration Registers Remote Configuration Registers The remote configuration registers listed in Table 25 are the same registers as previously described, but they are for the remote VLYNQ device. Note: Before attempting to access the remote registers (offsets 80h through C0h) , you must ensure that a link is established with the remote device. -
Page 39: Appendix A Vlynq Protocol Specifications
www.ti.com Appendix A Appendix A VLYNQ Protocol Specifications VLYNQ relies on 8b/10b block coding to minimize the number of serial pins and allow for in-band packet delineation and control. The following sections include general 8b/10b coding definitions and their implementation. Special 8b/10b Code Groups Table A-1. -
Page 40: Vlynq 2.0 Packet Format
www.ti.com VLYNQ 2.0 Packet Format A.2.1 Idle (/I/) The idle ordered sets are transmitted continuously and repetitively whenever the serial interface is idle. Idle is also used in the place of the flowed code in VLYNQ versions 2.0 and later. A.2.2 End of Packet (/T/) An end of packet delimiter delineates the ending boundary of a packet. -
Page 41: Packet Format (10-Bit Symbol Representation) Description
www.ti.com VLYNQ 2.0 Packet Format Table A-3. Packet Format (10-bit Symbol Representation) Description Field Value Description PKTTYPE[3:0] This field indicates the packet type. 0000 Reserved 0001 Write with address increment. 0010 Reserved 0011 Write 32-bit word with address increment. 0100 Reserved 0101 Configuration write with address increment. -
Page 42: Vlynq 2.X Packets
www.ti.com VLYNQ 2.X Packets VLYNQ 2.X Packets An example of what can happen to a write burst due to remote and local FIFO state changes and the link pulse timer expiring is shown in Example A-1. This protocol can be extended to apply to multiple channels; therefore, the data return channel is logically isolated from the command channel. - Page 43 www.ti.com VLYNQ 2.X Packets A command, length, address, and start receive data from the idle stream. A flow enable was received for the command channel, but there is data to return, so the flow is followed by a channel 1 descriptor (the command for return data actually indicates a channel 1), and the channel 1 packet is now under way.
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Page 44: Appendix B Write/Read Performance
www.ti.com Appendix B Appendix B Write/Read Performance The following sections discuss the write versus read performance and how the throughput (read or write) should be calculated for a given data width and serial clock frequency. Note: The data and throughput calculations shown here are sample calculations for most ideal situations. -
Page 45: Scaling Factors
www.ti.com Write Performance Table B-1. Scaling Factors Burst Size in 32-bit words Data Bytes Overhead Bytes Scaling Factor 69.56% 82.05% 90.14% Table B-2. Expected Throughput (VLYNQ Interface Running at 76.5 MHZ and 99 MHZ) Interface Running at 76.5 MHZ Interface Running at 99 MHZ Burst Size in Number of VLYNQ Pins 32-bit Words... -
Page 46: Read Performance
www.ti.com Read Performance Read Performance Since reads must complete a transmit-remote read-receive cycle before starting another read transaction, the data throughput is lower as compared to writes. There is latency involved in reading the data from the remote device; and in some cases, a local latency in writing the returned data before the next read can start. - Page 47 TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products...
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