Block Diagrams - National Instruments NI-6587 Getting Started Manual

Table 3. NI 6587 DDC Connector Names and Descriptions (Continued)
Signal Name
DIO<0..15>+
DIO<0..15>-
PFI <1..4>+
PFI <1..4>-
SE_PFI<1..3>
GND
For more detailed information about the NI 6587 front panel connectors, refer to the NI 6587
Specifications.

Block Diagrams

Figures 4 through 8 show the data flow through the NI 6587. Single-ended data lines use
standard clock levels to interpret data as either a binary zero or a one in high-speed digital data
transfers. Differential data lines provide a low-noise, low-power, low-amplitude differential
method for high-speed digital data transfer.
Pin(s)
14, 17, 20, 23, 26,
29, 32, 35, 38, 41,
44, 47, 50, 53, 56, 59
15, 18, 21, 24, 27,
30, 33, 36, 39, 42,
45, 48, 51, 54, 57, 60
2, 5, 8, 11
3, 6, 9, 12
68, 71, 72
1, 4, 7, 10, 13, 16,
19, 22, 25, 28, 31,
34, 37, 40, 42, 46,
49, 52, 55, 58, 69
Figure 4. Clock Input Signal
Global Clock to
NI FlexRIO FPGA Module
(UserGclkLvttl)
Signal Type
Data Positive differential terminal for the
bidirectional digitial I/O data
channels 0 through 15.
Data Negative differential terminal for
the bidirectional digital I/O data
channels 0 through 15.
Control Positive differential terminals for
bidirectional PFI channels 1
through 4.
Control Negative differential terminals for
bidirectional PFI channels 1
through 4.
Control Single-ended terminals for
bidirectional PFI channels 1
through 3.
Ground Ground reference for signals.
NI 6587 Getting Started Guide | © National Instruments | 7
Signal Description
CLOCK IN