National Instruments NI-6587 Getting Started Manual page 13

CLIP Name
•
NI 6587
Serdes
Connector •
3
CLIP
•
•
•
•
The following table lists the NI 6587 SMA connector signals and corresponding NI FlexRIO
FPGA module signals necessary for designing custom component-level IP (CLIP).
Table 5. NI 6587 SMA Signals and NI FlexRIO FPGA Module Signals
NI 6587
Signal Name
PFI 0
CLOCK IN
The following table lists the NI 6587 DDC connector signals and corresponding NI FlexRIO
FPGA module signals necessary for designing custom component-level IP (CLIP). The _CC
suffix on signals identifies channels that can receive a regional clock.
3
This CLIP is compatible only with LabVIEW 2010 and later.
12 | ni.com | NI 6587 Getting Started Guide
Table 4. NI 6587 CLIP Items (Continued)
Signals
Sixteen bidirectional
data LVDS lines
Four LVDS PFI lines
One LVDS STROBE
line
One LVDS clock output
signal
Four single-ended PFI
lines
One single-ended clock
input signal
GPIO Input
GPIO_2_n
GClk_SE
Provides read/write access to all LVDS and
single-ended channels, where the channels are
grouped by connector. This CLIP conveys
parallel data at high speeds. You can access
the LVDS data and direction lines using a U16
data type, you can access the LVDS PFI lines
using a U8 data type, and you can access the
single-ended PFI lines using a Boolean
control. In the U8 data type, the top four bits
are unused. Each LVDS line, PFI line, and
clock output is connected to an OSERDES or
ISERDES block that serializes or deserializes,
respectively, the signal by a factor of six by
default. Therefore, with every regional clock
cycle, the NI 6587 reads or writes six samples
to or from the ISERDES or OSERDES
blocks. All OSERDES and ISERDES blocks
are set to double data rate (DDR) mode.
NI FlexRIO FPGA Module
GPIO Output
GPIO_5_n
—
Description
GPIO Direction
GPIO_6_n (as enable)
—