Renesas 8V19N882 Manual
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Renesas 8V19N882 Manual

Renesas 8V19N882 Manual

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8V19N882
Evaluation Board Manual
Description
This document describes following about the
8V19N882 Evaluation Board:
■
Basic hardware and GUI setup
■
Board power-up instructions
■
Instructions to get active output signals using a
provided configuration file
■
Hardware modifications required for different
conditions
Features
The board has SMA connectors to relevant I/O of the
device.
■
Two differential clock inputs
■
16 differential outputs – Most outputs can be
configured to clock outputs or Sysref outputs
■
One different output for direct VCXO buffer
■
External VCXO
■
External footprint for VCO up to 6GHz
■
Selectable output buffer voltage
■
Laboratory power supply connectors
■
Serial port for configuration and register read out
Board Diagram
X0120315 Rev.1.0
Mar 30, 2021
Evalution Board Manual
PC Requirements
■
Renesas
Timing Commander Software
■
8V19N882
GUI
■
USB 2.0 or USB 3.0 Interface
■
Windows XP SP3 or later
■
Processor: Minimum 1GHz
■
Memory: Minimum 512MB; recommended 1GB
■
Available disk space:
●
Minimum 600MB (1.5GB 64-bit)
●
Recommended 1GB (2GB 64-bit)
■
Network access during installation if the .NET
framework is not currently installed on the system
Kit Contents
■
8V19N882 Evaluation Board
■
USB Type B Cable
■
Quick Start Guide
installed
Page 1
© 2021 Renesas Electronics

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Summary of Contents for Renesas 8V19N882

  • Page 1 8V19N882 Evaluation Board Manual Description PC Requirements ■ This document describes following about the Renesas Timing Commander Software installed 8V19N882 Evaluation Board: ■ 8V19N882 ■ ■ Basic hardware and GUI setup USB 2.0 or USB 3.0 Interface ■ ■ Board power-up instructions Windows XP SP3 or later ■...

  • Page 2: Table Of Contents

    Ordering Information ........................... 18 Revision History ............................18 Figures Figure 1. Labeled Board Image ..........................5 Figure 2. 8V19N882 Evaluation Board (Top) ......................12 Figure 3. 8V19N882 Evaluation Board (Bottom) ....................13 Figure 4. Example Configuration Phase Noise ....................... 17 X0120315 Rev.1.0...

  • Page 3: Functional Description

    The evaluation kit supports evaluation process of the 8V19N882NVGI, a fully integrate FemtoClock RF Sampling Clock Generator and Jitter Attenuator. The device also supports JESD204B/C. The 8V19N882 is two stage PLL architecture. The first stage PLL use external VCXO and the second stage has option to use either internal VCO or external VCO.
  • Page 4 8V19N882 Evaluation Board Manual Jumper Label Default Orientation VREG_3.3V, VREG_IN, VREG_EN VREG_1.8V VDDO18 JP10 VDD_SPI Between the left most pin and the center. JP12 VDD_OSCI Between VDD33_OSCI and 3.3V JP13 EXT_VCSO_PWR JP14 VCXO_PWR JP15 VREG_OUT, VREG_3.3V, VDD_RAA_3V3 Between VDD_RAA_3V3 and VREG_3.3V...

  • Page 5: Prepare The Software

    8V19N882 Evaluation Board Manual Figure 1. Labeled Board Image 1.2.2. Prepare the Software 1. Prior to execution of the GUI, the Timing Commander software must be downloaded and installed. If Timing Commander is already installed on the computer, skip this step.

  • Page 6: Bring Up The Gui

    8V19N882 Evaluation Board Manual 1.2.3. Bring Up the GUI 1. After successfully installing the Timing Commander software, activate the software from the Window <start> at the bottom left-corner of the screen. 2. Start > IDT > Timing Commander. 3. Click <Open Setting File>.
  • Page 7 8V19N882 Evaluation Board Manual 4. For the first-time use, if the proper part number does not appear, click the < Browse> button and choose the settings file from the current working directory. 5. Select the example Timing Commander Settings file (.tcs) from the current working directory.
  • Page 8 8V19N882 Evaluation Board Manual 6. Click the < Browser> button to the choose Personality file from the folder. The latest version of the Timing Commander Personality file (.tcp) can be downloaded from the 8V19N882 webpage. 7. Pick the personality file (.tcp) from the current working directory and click <Open>.

  • Page 9: Configure The Evaluation Board

    8V19N882 Evaluation Board Manual 8. Set up example or similar GUI appear as below. Frequencies can be varied (roll the mouse wheel to zoom in/out the display). If needed, the parameters can be modified (e.g., frequencies for input, output, VCO, output driver, charge pump, mux select, etc.).
  • Page 10 8V19N882 Evaluation Board Manual 2. Click the arrow pointed down to the chip to write the data to the DUT registers 3. Click the <Initialize DUT> to activate the clock output X0120315 Rev.1.0 Page 10 Mar 30, 2021...

  • Page 11: Sysref Setup

    8V19N882 Evaluation Board Manual 1.2.5. Sysref Setup 1. Assign output a Sysref Output by select the mux. 2. Set the dividers to generate the desired Sysref frequency. 3. Uncheck the power-down Sysref (PD SYSREF). 4. Click Sysref Generator Block to open the pop-out window.

  • Page 12: Board Design

    8V19N882 Evaluation Board Manual 2. Board Design Figure 2. 8V19N882 Evaluation Board (Top) X0120315 Rev.1.0 Page 12 Mar 30, 2021...

  • Page 13: Schematic Diagrams

    8V19N882 Evaluation Board Manual Figure 3. 8V19N882 Evaluation Board (Bottom) Schematic Diagrams For the schematic diagrams, see the end of this document. X0120315 Rev.1.0 Page 13 Mar 30, 2021...

  • Page 14: Bill Of Materials

    8V19N882 Evaluation Board Manual Bill of Materials Manufacturer Item Reference Part Part Number C1,C2,C3,C7,C8,C9,C23,C24,C27,C26,C3 2,C35,C43,C44,C45,C46,C47,C48,C49,C5 0,C51,C52,C56,C58,C59,C61,C63,C64,C6 0.1u GRM155R71C104KA88D 5,C66,C67,C68,C69,C70,C71,C72,C73,C7 4,C78,C81 C4,C10,C12,C13,C14,C15,C18,C19,C20,C 25,C28,C30,C34,C40,C41,C92,C104,C116 0.1u GRM155R71C104KA88D ,C125,C150,C152,C154 C5,C6,C11,C17,C21,C22,C29,C31,C151,C 100p GRM1555C1H101JA01D 153,C155 0 Ohm RMCF0402ZT0R00 CC0402JRNPO9BN330 C36, C158, C161, C170 EMK105BJ105KV-F CL05A226MQ5QUNC C79,C84...
  • Page 15 8V19N882 Evaluation Board Manual Manufacturer Item Reference Part Part Number TSW-105-07-F-S (or TSW- JP1,JP6, JP19 Header_5Pin 103-07-F-S + TSW-102-07- F-S) JP3,JP4,JP5,JP8,JP9,JP13, JP16, JP18, Header_2Pin TSW-102-07-F-S JP22, JP23,JP14 JP10, JP15, JP17, JP21 LVL_SHIFT_EN TSW-103-07-F-S JP12 VDD_OSCI TSW-103-07-F-S J1,J2,J4,J5,J6,J7,J11,J12,J13,J14,J16,J18 ,J22,J23,J24,J25,J26,J27,J29,J30,J31,J32, SMA_END_LAUNCH_PC 142-0701-801...
  • Page 16 8V19N882 Evaluation Board Manual Manufacturer Item Reference Part Part Number ERJ-2RKF2001X R92,R93 ERJ-2RKF1800X RC1206JR-070RL R101,R102,R115,R116,R124,R129,R130, ESR03EZPJ2R0 R131 R140,R142,R144,R146,R165 ERJ-2RKF1000X R151 ERJ-2RKF33R0X R152 ERJ-3GEYJ681V R154 ERJ-3GEYJ471V R163,R164 ERJ-3GEYJ270V R167 1.5K ERJ-3GEYJ152V R170,R174,R175 RC0603FR-0710KL U9,U10, U16 TPS7A8300 TPS7A8300ARGRT LSF0204PWR_TSSOP14 LSF0204PWR ft2232_chip FT2232D...

  • Page 17: Typical Performance Graphs

    8V19N882 Evaluation Board Manual 3. Typical Performance Graphs The following figure shows example phase noise performance from the loaded example configuration. Figure 4. Example Configuration Phase Noise X0120315 Rev.1.0 Page 17 Mar 30, 2021...

  • Page 18: Ordering Information

    8V19N882 Evaluation Board Manual 4. Ordering Information Part Number Description 8V19N882-EVK 8V19N882 Evaluation Board 5. Revision History Revision Date Description Mar 30, 2021 Initial release. X0120315 Rev.1.0 Page 18 Mar 30, 2021...
  • Page 19 Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products.

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