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PG-FP5 V2.17
9. SPECIFICATIONS OF TARGET INTERFACE CIRCUITS
This chapter describes the target interface specifications (signals connected to the FP5 and the target system), by using
equivalent circuits.
Note: The internal voltage regulator generates the FP5_VDD and FP5_VDD2 voltages.
9.1. SO/TxD/IO3/FPDR/FPMD3, RESET and SCK/IO4/FPCK/FPMD4
SO/TxD/IO3/FPDR/FPMD3, SCK/IO4/FPCK/FPMD4 signal lines output C-MOS level signals. When a 78K0R,
78K0S/Kx1+, UPD78F9334, V850 (Single-wire UART), RH850 (1 wire UART), or R8C is used, the
SO/TxD/IO3/FPDR/FPMD3 signal line functions as an open-drain output. The RESET signal line is fixed to the low
level until a device command is executed. Though the output is momentarily at CMOS levels while a device command
is being executed, it is otherwise controlled to be high impedance (pulled up to the high level by a 1 k-ohm resistor) or
at the low level.
Pull-up control
circuit
Signal output
circuit
Self-testing circuit
or
signal input circuit
Figure 9.1 SO/TxD/IO3/FPDR/FPMD3, RESET
9.2. SI/RxD/FPDT and H/S
The SI/RxD/FPDT and H/S input signal voltages must not exceed the rated maximum voltage. However, for the RL78,
the SI/RxD/FPDT pin becomes an I/O pin, and it is open-drain output upon output. For the RX family and SuperH
family, the H/S signal line is C-MOS level output.
Self-testing circuit
or
Signal output circuit
Self-testing circuit
or
Signal input circuit
Figure 9.2 SI/RxD/FPDT and H/S Pins
R20UT2922EJ0500 Rev.5.00
Mar 29, 2019
SPECIFICATIONS OF TARGET INTERFACE CIRCUITS
FP5_V
DD
74LV125
FP5_V
DD
33 Ω
74LV125
FP5_V
DD
74LV125
¯¯¯¯¯¯ and SCK/IO4/FPCK/FPMD4 Pins
FP5_V
DD
33 Ω
74LV125
FP5_V
DD
74LV125
1 kΩ
Target System
FP5
100 kΩ
Target System
FP5
Signal
Signal
Page 122 of 163
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