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RAA3064002GFP/RAA3064003GFP
5.3
DC Characteristics
Table 5.3 DC Characteristics (1)
Conditions: T
= -40 to +105°C, AV
A
Item
High-level input
RESET#, CLK, SDI, SCLK,
voltage
CS#, PWMINA, PWMINB
Low-level input voltage RESET#, CLK, SDI, SCLK,
CS#, PWMINA, PWMINB
Input leakage current
RESET#, CLK, SDI, SCLK,
CS#, PWMINA, PWMINB
High-level output
ALARM#, SDO, COUT
voltage
Low-level output
ALARM#, SDO, COUT
voltage
High-level output
ALARM#, SDO, COUT
current
Low-level output
ALARM#, SDO, COUT
current
Input capacitance
RESET#, CLK, SDI, SCLK,
CS#, PWMINA, PWMINB
Bias pin output voltage BIAS2P5
Bias pin output current
BIAS2P5
Note Pin output currents (load-dependent) are not included.
Table 5.4 DC Characteristics (2)
Conditions: T
= -40 to +105°C, AV
A
Item
Power-saving state
During operation
Supply current for the shunt
current detection block
Note Pin output currents (load-dependent) are not included.
R03UZ0002EJ0120 Rev.1.20
Apr 05, 2021
= EV
= IOV
= 4.5 to 5.5 V, AV
DD
DD
DD
Symbol
V
IH
V
IL
|
IL
V
OH
V
OL
I
OH
I
OL
C
I
V
BIAS
I
BIAS
= EV
= IOV
= 4.5 to 5.5 V, AV
DD
DD
DD
Symbol
Condition
Initial state of the registers after the
I
PS
release from the reset state.
A 4-MHz clock is being input to the
CLK pin. Digital input pins other than
the CLK pin are fixed to the low
level. The analog input pins are left
open-circuit, with the exception of
those for the excitation current.
A 4-MHz clock is being input to the
I
CC
CLK pin. Digital input pins other than
the CLK pin are fixed to the low
level. The analog input pins are left
open-circuit, with the exception of
those for the excitation current.
I
CS
= EV
= IOV
SS
SS
Condition
Min.
0.8 x IOV
DD
-0.3
I
= -2 mA
IOV
- 0.8
OH
DD
I
= 2 mA
OL
= EV
= IOV
SS
SS
Min.
5. Electrical Characteristics
= 0 V
SS
Typ.
Max.
IOV
+ 0.3
DD
0.2 x IOV
DD
1.0
0.8
-2
2
15
2.5
100
= 0 V
SS
Typ.
Max.
Unit
420
650
20
40
2.0
2.8
Page 38 of 52
Unit
V
V
μA
V
V
mA
mA
pF
V
μA
μA
mA
mA
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