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RAA3064002GFP/RAA3064003GFP
2.3.4
Control Block
The control block consists of a reset generating circuit, an SPI interface, and registers. Operations are triggered by the
clock signal input through the CLK pin.
This block can be reset by any from among the following reset sources: RESET#, voltage detection reset, or software
reset. Table 2.1 shows the types of resets and sources. The reset generating circuit conveys the reset signals generated
by each type of reset within the IC.
The SPI interface has four signal pins, one each for the serial communications clock (SCLK), reception and transmission
of data in serial communications (SDI and SDO), and serial communications enable (CS#). Read and write access to
registers in this IC by an external device is handled through these pins.
For setting and reading the data in the registers, see 3.3 Access to the Registers.
Table 2.1
Types of Reset and Sources
Type of Reset
Reset by the RESET# pin
Voltage detection reset
Software reset
R03UZ0002EJ0120 Rev.1.20
Apr 05, 2021
Source
Signal on the RESET# pin being driven low
Excessive dropping of AVDD or IOVDD
Setting of the given bit in the SWRST register
2. Circuit Configuration
Page 15 of 52
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