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RAA3064002GFP/RAA3064003GFP
3.3
Access to Registers
Reading and writing to registers in this IC is handled by a host MCU via SPI communications where the MCU is the master
and this IC is a slave. Four lines are used for the interface: serial clock input (SCLK), serial data input and output (SDI and
SDO), and chip select input (CS#).
The SPI communications format is as follows. Communications that are not in this format are invalid.
Communication direction: Full-duplex transmission and reception
•
Data length: 16 bits (1 bit for R/W
•
Bit order: MSB first
•
Figure 3.1 shows the timing chart of writing to register (data input). Figure 3.2 shows the timing chart of reading registers
(data output).
CS#
1
2
SCLK
Hi-Z
SDI
R/W = 0
A6
L
SDO
An: Register address [6:0]
Dn: Write data [7:0]
: Sampling timing
CS#
1
2
SCLK
Hi-Z
SDI
R/W = 1
A6
SDO
An: Register address [6:0]
Dn: Read data [7:0]
: Sampling timing
R03UZ0002EJ0120 Rev.1.20
Apr 05, 2021
____
, 7 bits for the address, and 8 bits for transfer data)
3
4
5
6
A5
A4
A3
A2
Figure 3.1 Timing Chart of Writing to Registers
3
4
5
6
A5
A4
A3
A2
Figure 3.2 Timing Chart of Reading Registers
7
8
9
10
A1
A0 = 0
D7
D6
7
8
9
10
A1
A0 = 0
D7
D6
3. Control Registers
11
12
13
14
D5
D4
D3
D2
11
12
13
14
Hi-Z
D5
D4
D3
D2
15
16
Hi-Z
D1
D0
15
16
D1
D0
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