Crystal - Espressif Systems ESP32-H2 Series Hardware Design Manuallines

3 PCB Layout Design
• Four-layer PCB design is preferred. The power traces should be routed on the inner third layer whenever
possible. Vias are required for the power traces to go through the layers and get connected to the pins on
the top layer. There should be at least two vias if the main power traces need to cross layers. The drill
diameter on other power traces should be no smaller than the width of the power traces.
• The 3.3 V power traces, highlighted in yellow, are routed as shown in Figure 14. The width of the main
power traces should be no less than 20 mil. The width of the power traces for VDD3P3 pins should be no
less than 15 mil. Recommended width of other power traces is 10 mil.
• The ESD protection diode is placed next to the power port (circled in red in the top left quarter of Figure 14).
The power trace should have a 10 µF capacitor on its way before entering into the chip, and a 0.1 or 1 µF
capacitor could also be used in conjunction. After that, the power traces are divided into several branches
using a star-shape topology, which reduces the coupling between different power pins. Note that all
decoupling capacitors should be placed close to the corresponding power pin, and ground vias should be
added close to the capacitor's ground pad to ensure a short return path.
Notice:
In Figure 14, the 10 µF capacitor is shared by the analog power supply pin1 VDD3P3, pin2 VDD3P3, and the power
entrance since the analog power is close to the chip power entrance. If the chip power entrance is not near the
VDD3P3 pin, it is recommended to add a 10 µF capacitor to both the chip power entrance and the analog power
VDD3P3, and also reserve a 1 µF capacitor if space permits.
• Pin1 VDD3P3 and pin2 VDD3P3 analog power supply should be surrounded by ground copper. It is
required to add GND isolation between the pin1 VDD3P3, pin2 VDD3P3, power trace and the surrounding
GPIO and RF traces, and place vias whenever possible.
• The ground pad at the bottom of the chip should be connected to the ground plane through at least nine
ground vias.
• If you need to add a thermal pad EPAD under the chip on the bottom of the module, it is recommended to
employ a square grid on the EPAD, cover the gaps with ink, and place ground vias in the gaps, as shown in
Figure 14. This can avoid chip displacement caused by tin leakage and bubbles when soldering the
module EPAD to the substrate.

3.4 Crystal

Figure 15 and Figure 16 show the reference design of the crystal. The crystal can be either connected to the
ground or not in the top layer. If there is sufficient ground in the top layer, it is recommended not to connect the
crystal to the ground. This helps to reduce the value of parasitic capacitance and suppress temperature
conduction, which can otherwise affect the frequency offset. In addition, the following should be noted:
• Ensure a complete GND plane for the RF, crystal, and chip.
• The crystal should be placed far from the clock pin to avoid the interference on the chip. The gap should
be at least 1.8 mm. It is good practice to add high-density ground vias stitching around the clock trace for
better isolation.
• There should be no vias for the clock input and output traces, which means the traces cannot cross layers.
• Components in series to the crystal trace should be placed close to the chip side.
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ESP32-H2 Series Hardware Design Guidelines v0.5