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3.5.2 CAS Latency Time
This controls the latency between DDR RAM read command and the
time that the data actually becomes available. Leave this on the default
setting.
3.5.3 Active to Precharge Delay
This item allows you to select the value in this field, depending on
whether the board has paged DRAMs or EDO (extended data output)
DRAMs. The Choice: EDO 50ns, EDO 60ns,Slow, Medium, Fast, Turbo.
3.5.4 DRAM RAS# to CAS# Delay
In order to improve performance, certain space in memory is reserved for
ISA cards. This memory must be mapped into the memory space below
16MB. The Choice: 15M-16M, Disabled.
3.5.5 RAS# Precharge Time
This controls the idle clocks after issuing a precharge command to
DRAM. Leave this on the default setting.
3.5.6 System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at F0000h-
FFFFFh, resulting in better system performance. However, if any pro-
gram writes to this memory area, a system error may occur. The Choices:
Enabled, Disabled.
3.5.7 Video Bios Cacheable
Selecting Enabled allows caching of the video BIOS, resulting in better
system performance. However, if any program writes to this memory
area, a system error may occur. The Choices: Enabled, Disabled.
3.5.8 Memory Hole At 15M-16M
Enabling this feature reserves 15 MB to 16 MB memory address space
for ISA expansion cards that specifically require this setting. This makes
memory from 15 MB and up unavailable to the system. Expansion cards
can only access memory up to 16 MB. The default setting is "Disabled."
3.5.9 Delayed Transaction
The chipset has an embedded 32-bit posted write buffer to support delay
transactions cycles. Select Enabled to support compliance with PCI spec-
ification version 2.1. The Choice: Enabled, Disabled.
3.5.10 Delay Prior to Thermal
Select Enabled if user wants to lower the CPU speed when CPU tempera-
ture is too high. The choice: Enabled, Disabled.
PCA-6006 User's Manual
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