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BR-Automation X20CP1301 Manual

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X20(c)CP1301, X20CP1381 and X20CP1382
1 General information
Compact CPUs are available with processor speeds of 200 MHz and 400 MHz. Depending on the variant, up to
256 MB RAM and up to 32 kB nonvolatile onboard RAM is available. A built-in flash drive is available to store up
to 2 GB of application and other data.
All CPUs come equipped with Ethernet, USB and one RS232 interface. In both performance classes, integrated
POWERLINK and CAN bus interfaces are also available. If additional fieldbus connections are needed, the CPU
can be upgraded with an interface module from the standard X20 product range. These CPUs do not require fans
or batteries and are therefore maintenance-free. 30 different digital inputs and outputs and 2 analog inputs are
integrated in the devices. 1 analog input can be used for PT1000 resistance temperature measurement.
• CPU is Intel x86 200/400 MHz compatible with integrated I/O processor
• Ethernet, POWERLINK with poll-response chaining and USB onboard
• 1 slot for modular interface expansion
• 30 digital inputs/outputs and 2 analog inputs integrated in the device
• 1/2 GB flash drive onboard
• 128/256 MB DDR3 SDRAM
• Fanless
• No battery
• Battery-backed real-time clock
2 Coated modules
Coated modules are X20 modules with a protective coating for the electronics component. This coating protects
X20c modules from condensation and corrosive gases.
The modules' electronics are fully compatible with the corresponding X20 modules.
For simplification purposes, only images and module IDs of uncoated modules are used in this data
sheet.
The coating has been certified according to the following standards:
• Condensation: BMW GS 95011-4, 2x 1 cycle
• Corrosive gas: EN 60068-2-60, method 4, exposure 21 days
Data sheet V1.21
X20(c)CP1301, X20CP1381 and X20CP1382
1

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Summary of Contents for BR-Automation X20CP1301

  • Page 1 X20(c)CP1301, X20CP1381 and X20CP1382 X20(c)CP1301, X20CP1381 and X20CP1382 1 General information Compact CPUs are available with processor speeds of 200 MHz and 400 MHz. Depending on the variant, up to 256 MB RAM and up to 32 kB nonvolatile onboard RAM is available. A built-in flash drive is available to store up to 2 GB of application and other data.

  • Page 2: Order Data

    Model number Short description X20 CPUs X20CP1301 ZX20 CPU, with integrated I/O, x86-200, 128 MB DDR3 RAM, 16 kB FRAM, 1 GB onboard flash drive, 1 insert slot for X20 interface modules, 1 USB interface, 1 RS232 interface, 1 Ethernet interface 10/100BASE-T, 14 digital inputs, 24 VDC, sink, 4 digital inputs, 2 µs, 24 VDC, sink, 4...

  • Page 3: Technical Data

    X20(c)CP1301, X20CP1381 and X20CP1382 4 Technical data Model number X20CP1301 X20cCP1301 X20CP1381 X20CP1382 Short description Interfaces 1x RS232, 1x Ethernet, 1x USB, 1x X2X Link 1x RS232, 1x Ethernet, 1x POWER- LINK, 2x USB, 1x X2X Link, 1x CAN bus...
  • Page 4 X20(c)CP1301, X20CP1381 and X20CP1382 Model number X20CP1301 X20cCP1301 X20CP1381 X20CP1382 Processor Type Vx86EX Clock frequency 200 MHz 400 MHz L1 cache Data code 16 kB Program code 16 kB L2 cache 128 kB Integrated I/O processor Processes I/O data points in the background...
  • Page 5 X20(c)CP1301, X20CP1381 and X20CP1382 Model number X20CP1301 X20cCP1301 X20CP1381 X20CP1382 Input current at 24 VDC X1 - Standard inputs: Typ. 3.5 mA X2 - Standard inputs: Typ. 2.68 mA X2 - High-speed inputs: Typ. 3.5 mA X3 - Mixed channels: Typ. 2.68 mA...
  • Page 6 X20(c)CP1301, X20CP1381 and X20CP1382 Model number X20CP1301 X20cCP1301 X20CP1381 X20CP1382 Output of digital value during overload Configurable Conversion procedure Input filter 3rd-order low pass / cutoff frequency 1 kHz Max. error at 25°C Voltage Gain 0.18% (Rev. <C0: 0.37%) Offset 0.04% (Rev.
  • Page 7 X20(c)CP1301, X20CP1381 and X20CP1382 Model number X20CP1301 X20cCP1301 X20CP1381 X20CP1382 Pulse width modulation Period duration 5 to 65535 µs corresponds to 200 kHz to 15 Hz Pulse duration 0 to 100%, minimum 2.5 µs Resolution for pulse duration 0.1% of the configured frequency...

  • Page 8: Led Status Indicators

    X20(c)CP1301, X20CP1381 and X20CP1382 The high-speed digital outputs can be used for pulse width modulation. Only for standard outputs and mixed channels. Standard outputs and mixed channels: At loads ≤ 1 kΩ 5 LED status indicators 5.1 Slot X1 Figure Color Status Description...

  • Page 9: Error Message

    X20(c)CP1301, X20CP1381 and X20CP1382 5.1.1.2 POWERLINK V2 mode Error message LED "S/E" Green Description The interface is in the error mode (failed Ethernet frames, increased number of collisions on the network, etc.). Note: Several red blinking signals are displayed immediately after the device is switched on. These are not errors, however. Blinking If an error occurs in the following modes, then the green LED blinks over the red LED: •...
  • Page 10 X20(c)CP1301, X20CP1381 and X20CP1382 LED "S/E" Green Description Triple flash Mode: READY_TO_OPERATE (approx. 1 Hz) The interface is in mode READY_TO_OPERATE. Managing node (MN) Cyclic and asynchronous communication. Received PDO data is ignored. Controlled node (CN) The configuration of the CN is completed. Normal cyclic and asynchronous communication. The transmitted PDO data corre- sponds to the PDO mapping.
  • Page 11 X20(c)CP1301, X20CP1381 and X20CP1382 5.2 Slot X2 Figure Color Status Description 1 - 14 Green Input state of the corresponding digital input Table 5: LED status indicators on the integrated X2 I/O slot 5.3 Slot X3 Figure Color Status Description Yellow I/O power supply OK Everything OK...

  • Page 12: Operating And Connection Elements

    X20(c)CP1301, X20CP1381 and X20CP1382 6 Operating and connection elements X20CP1301 Integrated flash drive Top-hat rail Slot for locking mechanism interface module LED status indicators IF6 - X2X Link Connections for: - Power supplies - I/O channels - IF1 - RS232...

  • Page 13: Operating Mode

    X20(c)CP1301, X20CP1381 and X20CP1382 6.1 Button for reset and operating mode Figure 1: Button for reset and operating mode 6.1.1 Reset The button must be pressed for less than 2 seconds to trigger a reset. This triggers a hardware reset on the CPU, which means that: •...
  • Page 14 The INA2000 station number can be set using the Automation Studio software. Information about cabling X20 modules with an Ethernet interface can be found in the module's download section at (www.br-automation.com). Information: The Ethernet interface (IF2) is not suitable for POWERLINK (see "POWERLINK interface (IF3)"...

  • Page 15: Ethernet Mode

    X20(c)CP1301, X20CP1381 and X20CP1382 6.6 POWERLINK interface (IF3) Compact CPUs X20CP1381 and X20CP1382 are equipped with a POWERLINK V2 interface. POWERLINK By default, the POWERLINK interface is operated as a managing node (MN). In the managing node, the node number is set to a fixed value of 240. If the POWERLINK node is operated as a controlled node (CN), a node number from 1 to 239 can be set in the POWERLINK configuration in Automation Studio.
  • Page 16 X20(c)CP1301, X20CP1381 and X20CP1382 6.7 USB interfaces (IF4 and IF5) IF4 - USB IF5 - USB IF4 and IF5 are non-galvanically isolated USB interfaces. The connection is made via a USB interface (1.1/2.0). The USB interfaces can only be used for devices approved by B&R (e.g. floppy disk drive, DiskOnKey or dongle). Information: •...

  • Page 17: Terminating Resistor

    X20(c)CP1301, X20CP1381 and X20CP1382 6.8 CAN bus interface (IF7) With the exception of the entry level CPU, all compact CPUs are equipped with a non-electrically isolated CAN bus interface. It is located on the X1 I/O slot. 6.8.1 Pinout CAN high CAN low Figure 3: CAN bus interface (IF7) on the X1 I/O slot - Pinout 6.8.2 Terminating resistor...
  • Page 18 X20(c)CP1301, X20CP1381 and X20CP1382 6.10 Data and real-time clock buffering The CPUs do not use a battery. This makes them completely maintenance-free. The following measures make operation without a backup battery possible. Data and real-time clock buffering Type of buffering Note Remanent variables FRAM...

  • Page 19: Connection Example

    X20(c)CP1301, X20CP1381 and X20CP1382 Pinout +24 V CP/X2X L. +24 V I/O Figure 5: Integrated power supply - Pinout Connection example 10 A slow-blow CPU/X2X Link power supply power supply +24 VDC +24 VDC Figure 6: CPU supply - Connection example 8 Overtemperature cutoff To prevent damage, a shutdown/reset is triggered on the CPU when the processor reaches 95°C.

  • Page 20: Digital Inputs/Outputs

    X20(c)CP1301, X20CP1381 and X20CP1382 9 Local I/O channels Compact CPUs are equipped with 3 integrated I/O slots. These devices have 30 digital inputs/outputs and 2 analog inputs. Information about the functions of the high-speed digital inputs and outputs can be found in the section "Functions of the high-speed digital inputs/outputs"...
  • Page 21 X20(c)CP1301, X20CP1381 and X20CP1382 10 Pinouts Slot X1 AI + 1 I AI + 2 I AI + 1 U / Sensor + AI + 2 U AI - 1 U/I / Sense - AI - 2 U/I DI 1 DI 2 DI 3 DI 4...
  • Page 22 X20(c)CP1301, X20CP1381 and X20CP1382 Slot X3 To ensure proper operation of the digital mixed channels (DI 5 / DO 5 to DI 8 / DO 8), it is important to observe the notes in section "Power supply concept of Compact CPUs" on page To prevent crosstalk, each signal line of the high-speed digital outputs should be shielded individually.

  • Page 23: Connection Examples

    X20(c)CP1301, X20CP1381 and X20CP1382 11 Connection examples 11.1 Slot X1 Voltage/Current measurement, digital inputs and CAN bus Voltage Current measurement measurement Sensor 1 Sensor 2 Sensor 3 Sensor 4 CAN high CAN low +24 VDC +24 VDC +24 VDC Figure 10: Connection example 1 for integrated X1 I/O slot PT1000 resistance temperature measurement, voltage measurement, digital inputs and RS232 PT1000 Resistance...
  • Page 24 X20(c)CP1301, X20CP1381 and X20CP1382 11.2 Slot X2 Digital inputs and ABR incremental encoder Sensor 1 Sensor 2 Sensor 3 Sensor 4 Sensor 5 Sensor 6 Sensor 7 Sensor 8 Sensor 9 Sensor 10 +24 VDC +24 VDC +24 VDC +24 VDC Figure 12: Connection example 1 for integrated X2 I/O slot Observe the wiring guidelines from the encoder manufacturer.
  • Page 25 X20(c)CP1301, X20CP1381 and X20CP1382 11.3 Slot X3 Digital inputs/outputs, direction/frequency (DF), PWM, CPU / X2X Link power supply and I/O power supply Actuator 1 Actuator 2 Actuator 3 Actuator 4 Actuator 5 Sensor 6 Actuator 7 Sensor 8 10 A slow-blow CPU/X2X Link power supply power supply...
  • Page 26 X20(c)CP1301, X20CP1381 and X20CP1382 12 Functions of the high-speed digital inputs/outputs 12.1 Functions of the high-speed digital inputs Possible functions The high-speed digital inputs DI 11 to DI 14 can be configured for the following functions: It is important to note that maximum 2 functions of the same type are possible with edge detection.
  • Page 27 X20(c)CP1301, X20CP1381 and X20CP1382 12.2 Functions of the high-speed digital outputs Possible functions The high-speed digital outputs DO 9 to DO 12 can be configured for the following functions: Channel Function DO 9 PWM - Pulse width modulation D - Direction DO 10 PWM - Pulse width modulation F - Frequency...

  • Page 28: Digital Outputs (X3)

    X20(c)CP1301, X20CP1381 and X20CP1382 13 Input/Output circuit diagram 13.1 Digital inputs (X1) and high-speed digital inputs (X2) DI x I/O status LED (green) Input status Figure 15: Input circuit diagram of the digital inputs on the integrated X1 I/O slot and the high-speed digital inputs on the integrated X2 I/O slot 13.2 Digital inputs (X2) DI x I/O status...
  • Page 29 X20(c)CP1301, X20CP1381 and X20CP1382 13.4 High-speed digital outputs (X3) Push-Pull Output status Logic DO x Output monitoring I/O status LED (orange) Figure 18: Output circuit diagram of the high-speed digital outputs on the integrated X3 I/O slot 13.5 Digital inputs/outputs (X3) To ensure proper operation of the digital mixed channels (DI 5 / DO 5 to DI 8 / DO 8), it is important to observe the notes in section "Power supply concept of Compact CPUs"...
  • Page 30 X20(c)CP1301, X20CP1381 and X20CP1382 13.7 Encoder power supply (X2) Protective equipment +24 V encoder Figure 21: Circuit diagram of the encoder supply on the integrated X2 I/O slot 13.8 CPU, X2X Link and I/O power supply (X3) Input status +24 V I/O DC OK +24 V CPU/X2X L.
  • Page 31 X20(c)CP1301, X20CP1381 and X20CP1382 14 Switching frequency derating for high-speed digital outputs The high-speed digital outputs can be switched with a frequency of max. 200 kHz. Derating may be necessary depending on the mounting orientation and operating temperature. Switching frequency derating for horizontal mounting orientations Operating temperature [°C] Figure 23: Switching frequency derating for high-speed digital outputs with horizontal mounting orientations Switching frequency derating for vertical mounting orientations...

  • Page 32: Switching Inductive Loads

    X20(c)CP1301, X20CP1381 and X20CP1382 15 Switching inductive loads 100 H 10 H 1000 Switching voltage: 28.8 V 24.0 V 100 mH Coil resistance Coil inductance [Ω] 10 mH Max. switching cycles / second (with 90% duty cycle) Information: If the maximum number of operating cycles per second is exceeded, an external inverse diode must be used.

  • Page 33: Register Description

    X20(c)CP1301, X20CP1381 and X20CP1382 16 Register description 16.1 System requirements The following minimum versions are recommended to generally be able to use all functions: • Automation Studio 4.1.4.96 • Automation Runtime M4.10 for X20cCP1301 • Automation Runtime D4.09 for all other variants 16.2 General data points This CPU is equipped with general data points.
  • Page 34 X20(c)CP1301, X20CP1381 and X20CP1382 16.3.1 Digital inputs Unfiltered The input status is recorded in a 100 µs cycle. Filtered The filtered status is transferred in a 100 µs cycle. Filtering takes place asynchronously in an interval of 100 μs. 16.3.1.1 Digital input filter Name: X1CfO_DI_Filter This register can be used to specify the filter value for all digital inputs.
  • Page 35 X20(c)CP1301, X20CP1381 and X20CP1382 16.3.2 Analog inputs Analog input values are recorded in a fixed interval. The time required for conversion/updating depends on the number of analog inputs and on the input signal: Input signal Time required for conversion/updating 1 current/voltage input 100 µs 1 temperature/resistance input 200 µs...

  • Page 36: Input Filter

    X20(c)CP1301, X20CP1381 and X20CP1382 16.3.2.3 Input filter The analog inputs are equipped with a configurable input filter. 16.3.2.3.1 Input ramp limitation Input ramp limitation can only take place when a filter is used; the input ramp is limited before filtering takes place. The amount the input value changes is checked to make sure that specified limits are not exceeded.

  • Page 37: Filter Level

    X20(c)CP1301, X20CP1381 and X20CP1382 Example 2 A disturbance interferes with the input value. The diagram shows the adjusted input value with the following settings: Input ramp limitation = 4 = 0x07FF = 2047 Filter level = 2 Eingangswert intern nachgeführter Eingangswert vor dem Filter 16000 Störung (Spike) 8000...
  • Page 38 X20(c)CP1301, X20CP1381 and X20CP1382 The following examples show how filtering works in the event of an input jump or disturbance. Example 1 The input value jumps from 8000 to 16000. The diagram shows the calculated value with the following settings: Input ramp limitation = 0 Filter level = 2 or 4 Input value...

  • Page 39: Channel Type

    X20(c)CP1301, X20CP1381 and X20CP1382 16.3.2.3.3 Configuring the input filter Name: X1CfO_AI1_Filter X1CfO_AI2_Filter This register is used to define the filter level and input ramp limitation of the input filter. Data type Values USINT See the bit structure. Bit structure: Description Value Information 0 - 2...
  • Page 40 X20(c)CP1301, X20CP1381 and X20CP1382 16.3.2.5 Limit values The input signal is monitored at the upper and lower limit values. By default the following limits are set for each mode: Limit value (default) Voltage signal ±10 V Current signal 0 to 20 mA Current signal 4 to 20 mA Upper maximum limit value 10 V...
  • Page 41 X20(c)CP1301, X20CP1381 and X20CP1382 16.4 Register overview of the I/O data points on the integrated X2 I/O slot Register Name Data type Read Write Cyclic Acyclic Cyclic Acyclic X2 - Configuration 7168 X2CfO_EdgeDetectUnit01Mode USINT ● 7169 X2CfO_EdgeDetectUnit01Master USINT ● 7170 X2CfO_EdgeDetectUnit01Slave USINT ●...
  • Page 42 X20(c)CP1301, X20CP1381 and X20CP1382 16.4.1 Digital inputs Unfiltered The input status is recorded in a 100 µs cycle. Filtered The filtered status is transferred in a 100 µs cycle. Filtering takes place asynchronously in an interval of 100 μs. 16.4.1.1 Digital input filter Name: X2CfO_DI_Filter This register can be used to specify the filter value for all digital inputs.

  • Page 43: Edge Detection

    X20(c)CP1301, X20CP1381 and X20CP1382 16.4.2 Edge detection Digital inputs 11 to 14 can be used for high-speed edge detection. This runs parallel to all other functions such as counters, etc. This function does not use the digital input filter. The edge detection function measures edges with µs precision. 2 units are available. A master and a slave edge can be configured for each unit.
  • Page 44 X20(c)CP1301, X20CP1381 and X20CP1382 16.4.2.3 Edge detection unit - Selection of slave edge Name: X2CfO_EdgeDetectUnit01Slave X2CfO_EdgeDetectUnit02Slave These registers are used to select the source of the slave edge for the respective unit. Either the rising or falling edge of one of the 4 high-speed digital input channels can be selected. Only one edge can be selected for each unit. Data type Value Information...

  • Page 45: Counter Functions

    X20(c)CP1301, X20CP1381 and X20CP1382 16.4.3 Counter functions High-speed digital inputs 11 to 14 can be used for counter functions. This function does not use the digital input filter. The following functions are available. Only one of these basic configurations can be enabled at a time: •...
  • Page 46 X20(c)CP1301, X20CP1381 and X20CP1382 16.4.3.3 Configuring the latch signals Name: X2CfO_Latch01Comparator X2CfO_Latch02Comparator This register defines the inputs and their level for triggering the latch procedure. • This defines which inputs are linked to generate the latch event. All 4 digital input signals can be used for an "AND"...
  • Page 47 X20(c)CP1301, X20CP1381 and X20CP1382 16.4.3.6 Latched counter value Name: Counter01Latch Counter02Latch As soon as the latch conditions have been met, the value of the respective counter is copied to these registers. Data type Value Information DINT -2,147,483,648 to 2,147,483,647 Latched counter value 16.4.3.7 Counter value of latch events Name: Latch01Count...
  • Page 48 X20(c)CP1301, X20CP1381 and X20CP1382 16.5 Register overview of the I/O data points on the integrated X3 I/O slot Register Name Data type Read Write Cyclic Acyclic Cyclic Acyclic X3 - Configuration 10240 X3CfO_DI_Filter USINT ● 10752 X3CfO_Mov01Mode USINT ● 10756 X3CfO_Mov01SpeedLimit UDINT ●...

  • Page 49: Physical Configuration

    X20(c)CP1301, X20CP1381 and X20CP1382 16.5.1 Physical configuration of I/O channels These registers are used to define the functionality of the channels. Depending on the desired configuration, the following assignments can be made with respect to the existing software and hardware: •...
  • Page 50 X20(c)CP1301, X20CP1381 and X20CP1382 16.5.2 Monitoring of the I/O power supply voltage Name: StatusInput01 The status of the I/O power supply voltage is . Data type Value Information USINT I/O power supply voltage within permitted range I/O power supply voltage not connected or outside of the permitted range 16.5.3 Digital inputs Unfiltered The input status is recorded in a 100 µs cycle.

  • Page 51: Digital Outputs

    X20(c)CP1301, X20CP1381 and X20CP1382 16.5.4 Digital outputs The output status is processed in a 100 µs cycle. 16.5.4.1 Switching state of digital outputs 1 to 12 Name: DigitalOutput01 to DigitalOutput12 These registers are used to store the switching state of digital outputs 1 to 12. Data type Values USINT...
  • Page 52 X20(c)CP1301, X20CP1381 and X20CP1382 16.5.5 Monitoring status of the digital outputs The error states of the outputs must be programmed in the application. The status information that is read is the actual voltage state on the channel (set or reset). The error state is therefore determined by a difference between the data points "DigitalOutputxx"...
  • Page 53 X20(c)CP1301, X20CP1381 and X20CP1382 16.5.6 Pulse width modulation (PWM) function Digital inputs 9 to 12 can be configured as PWM outputs. 2 data points are available per channel for controlling the PWM signal. Pulsbreite 24 VDC Periode (Frequenz) Figure 29: The PWM signal is controlled by setting the pulse width and period duration 16.5.6.1 Period duration of the PWM outputs Name: PWMPeriod09 to PWMPeriod12...
  • Page 54 X20(c)CP1301, X20CP1381 and X20CP1382 16.5.7 DF movement generator function Digital output channels 9 to 12 can be configured as 2 independently functioning movement generators (Direc- tion/Frequency) for stepper motor control. The movement generators are assigned to the following channels: Movement generator Channel Function DO 9...

  • Page 55: Edge Mode

    X20(c)CP1301, X20CP1381 and X20CP1382 16.5.7.1 Configuring the movement mode Name: X3Cfo_Mov01Mode X3Cfo_Mov02Mode These registers are used to configure how the speed setpoint is interpreted. The difference between the two modes is whether edges or periods are output for each increment of the setpoint. Data type Value Information...
  • Page 56 X20(c)CP1301, X20CP1381 and X20CP1382 16.5.7.2 Configuring the maximum speed of the movement The maximum speed or output frequency of the movement is configured in order to protect the digital output, the actuator/drive being controlled and/or the mechanical system. Name: X3Cfo_Mov01SpeedLimit X3Cfo_Mov02SpeedLimit These registers are used to configure the maximum speed / output frequency permitted in the system.
  • Page 57 X20(c)CP1301, X20CP1381 and X20CP1382 16.5.7.4 Speed and direction control of the movement The following parameters are important for speed and direction control of the movement: Characteristic value Description Speed control The predefined speed is specified as a percentage of the configured maximum speed. 0 to ±32767 correspond to 0 to ±100% of the configured maximum speed Direction control The direction of movement is defined by the sign of the speed setpoint:...

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