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Basic Test Procedure
Figure 7. TSW3100 CommsSignalPattern (WCDMA) Programming GUI
3.4
AFE7070 Software Quick-Start Guide
•
Select the AFE7070 tab, and press the Reset USB Port button.
•
In the Clock Settings section, set the clock mode to Dual Input Clock.
•
If the LVDS output is not connected to anything, disable it using the LVDS Power Down switch under
the Power heading.
•
Select the CDCM7005 tab to adjust the output clock signals:
– Y1 (AFE7070's CLK_IO) must be LVCMOS, with Y1A set to active rather than 3-state.
– Y3 (AFE7070's DACCLK) must be LVPECL, with both Y3A and Y3B set to active.
– Y4 (CDC Out) must be LVCMOS, with Y4A set to active.
•
Press the Send All button in the Register Controls section.
•
Monitor the RF output signal on a spectrum analyzer.
•
Monitor the output signal at the RF output connector. If the LO input frequency is set to 2 GHz and the
digital inputs are configured to be tones at 1.5 MHz and 2.5 MHz, the RF output looks like two tones
placed at 2001.5 MHz and 2002.5 MHz as seen in
10
AFE707xEVM Evaluation Module
Figure
Copyright © 2012, Texas Instruments Incorporated
8.
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SLOU337 – March 2012
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