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The following is a reference circuit design for 3-camera applications.
VPH_PWR
VPH_PWR
CAM0_ RST
CAM0_PWDN
CAM0_MCLK
CAM0_I2C_SDA
CAM0_I2C_SCL
CSI0_LN3_P
CSI0_LN3_N
CSI0_LN2_P
CSI0_LN2_N
CSI0_LN1_P
CSI0_LN1_N
CSI0_LN0_P
CSI0_LN0_N
CSI0_ CLK_P
CSI0_ CLK_N
CAM1_ RST
CAM1_ PWDN
CAM1_ MCLK
CSI1_ CLK_P
CSI1_ CLK_N
CSI1_LN0_P
CSI1_LN0_N
CSI1_LN1_P
CSI1_LN1_N
CSI1_LN2_P
CSI1_LN2_N
CSI1_LN3_P
CSI1_LN3_N
CAM2_RST
CAM2_PWDN
CAM2_MCLK
CAM1_I2C_SDA
CAM1_I2C_SCL
Figure 22: Reference Circuit Design for 3-Camera Applications
NOTE
In 3-camera applications, CSI1_LN3_P and CSI1_LN3_N are used as MIPI clock signals of camera 2.
CSI1_LN2_P and CSI1_LN2_N are used as MIPI data signals of camera 2.
SC206E_Series_Hardware_Design
1 μF
VPH_PWR
GPIO
1 μF
LDO
IN
GPIO
EN
1 μF
LDO
IN
GPIO
EN
_
_
AF_VDD
LDO
IN
OUT
EN
GND
VDD_2V8
OUT
GND
OUT
GND
LDO15A_1V8
EMI
EMI
EMI
EMI
EMI
1 μF
4.7 μF
1μF
EMI
EMI
EMI
μF
4.7
1μF
EMI
EMI
2.2K
2.2K
Smart Module Series
AVDD
DVDD
DOVDD
DOVDD
AVDD
DVDD
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