Quectel SC206E Series Hardware Design page 45

USB_SS2_RX_P 152
USB_SS2_RX_M 192
USB_SS2_TX_P 150
USB_SS2_TX_M 151
USB_CC1 249
USB_CC2 246
Module
USB_VBUS
USB_DP
USB_DM
USB_CC1
USB_CC2
USB _ SS1 _RX _P
USB _ SS1 _RX _M
USB _ SS1 _TX_P
USB _ SS1 _TX_M
USB _ SS2 _RX _P
USB _ SS2 _RX _M
USB _ SS2 _TX_P
USB _
SS2
_TX_M
Figure 12: USB Interface Reference Design (OTG Supported)
In order to ensure USB performance, comply with the following principles when designing the USB
interface.
⚫
Route the USB signal traces as a differential pair with total grounding. The impedance of USB
differential trace should be controlled to 90 Ω.
⚫
Keep the ESD protection component as close as possible to the USB connector. Pay attention to the
influence of junction capacitance of ESD protection component on USB data lines. Typically, the
capacitance value should be less than 2 pF for USB 2.0 and less than 0.5 pF for USB 3.1.
⚫
Do not route signal traces under crystals, oscillators, magnetic devices or RF signal traces. Route
the USB differential traces in inner-layer with ground shielding on not only the upper and lower
layers but also the right and left sides.
⚫
Make sure the intra-pair length difference within USB 2.0 differential pair does not exceed 2 mm,
and that within USB 3.1 Rx or Tx differential pair does not exceed 0.7 mm.
⚫
The spacing between USB signals and all other signals should be at least 4 times the trace width
while the signals between Rx and Tx should be at least 3 times the trace width.
SC206E_Series_Hardware_Design
AI USB 3.1 channel 2 superspeed receive (+)
AI USB 3.1 channel 2 superspeed receive (-)
AO USB 3.1 channel 2 superspeed transmit (+)
AO USB 3.1 channel 2 superspeed transmit (-)
AI USB Type-C detect 1
AI USB Type-C detect 2
Smart Module Series
-
-
C1
C2
C3
C4
C5
C6
C7
C8
USB Type-C
VBUS
D+
D-
CC1
CC2
RX1+
RX1-
TX1+
TX1-
RX2+
RX2-
TX2+
TX2-
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