Silicon Laboratories C8051F064-EK User Manual page 8

C8051F064-EK
7.5. Analog Inputs (J4, J5, J6, J8, J16, ADC0 [J13], ADC1 [J12])
Two BNC connectors (J13 (ADC0) and J12 (ADC1)) are provided on the C8051F064 board for easy evaluation of
the 16-bit on-chip ADCs. These analog inputs can be used to input an ac analog signal to the ADCs, ADC0 and
ADC1. Additionally, front-end circuitry is provided to condition the analog signals. To use this circuitry, follow the
guidelines listed below in conjunction with the schematic located in Section 8 "Schematics". See "AN190:
Understanding ADC Specifications" for a detailed discussion of issues related to ADC performance.
Select the 5 V supply voltage for the Voltage References U3 and U6 at header J4. Place a shorting block on J4,
pin1 and pin2, to select the DATA VBUS signal. Place a shorting block on J4, pin2 and pin3, to select the
DEBUG VBUS signal.
A single-supply voltage option is provided on the evaluation board for the op-amps. Place a shorting block on J6
to connect the "V+" op-amp supply to AV+. Additionally, place a shorting block on J8 to connect the "V–"
op-amp supply to GND.
Provide a dual-supply voltage to the op-amps for optimal performance by removing the shorting blocks on
headers J6 and J8. To supply the voltages, +5 V and –5 V signals will need to be provided at the J3 terminal
block (pin1 and pin2).
Note: Remove shorting blocks from J6 and J8 BEFORE applying voltages to the J3 terminal block. Voltages applied to J3
while shorting blocks are on J6 and J8 could cause damage to the evaluation board.
Provide an external Conversion Start signal to ADC0 at header J5 pin1.
Provide an external Conversion Start signal to ADC1 at header J5 pin2.
Differential measurement from one test source: input signal to ADC0 and place shorting block on header J16.
7.6. Analog I/O (Terminal Block [J3])
J3 is used to provide off-board voltage supply and voltage references for better noise performance evaluation in a
lab environment. Refer to Table 3 for terminal block connections.
7.7. External Memory Interface (J11, J14)
The C8051F064 evaluation board provides an External Memory Interface by connecting a 128 kB SRAM to the
device port pins. The device's External Memory Interface can be enabled by installing a shorting block at header
J11. This connects port pin P4.5 to the Chip Select (CS) signal on the SRAM, pulling this signal low. Placing a
shorting block on header J14, pin2 and pin3, enables the use of the lower address bank on the SRAM. Moving the
shorting block to J14, pin1 and pin2, enables port pin P3.7 to select between the upper and lower address banks
on the SRAM. Refer to Table 4 for the external memory interface signal descriptions.
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Table 3. Terminal Block (J3) Pin Descriptions
Pin # Description
1
2
3
4
5 +3.3 VIN
6
Rev. 0.2
–5 V
+5 V
AGND
GND
5VDD