Figure 13 Typical Power On Sequence (Using External Processor) - Enfora Enabler II-G Integration Manual

Integration Guide
Version 1.01
Figure 12 shows a typical power on sequence for the CPU to GSM0108 interface. Note that RADIO_PWR/RST is
not used, and the I/O and serial voltage levels are not a concern.
Power On Sequence
BATT
D.C.
RADIO_PWR/RST
50ms
PWR_CTL_SIGNAL D.C.
I/O level
don't care
Serial level
don't care
System State
Figure 12 Typical Power On Sequence (using external processor)
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