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Theory of Operation
4-33.
SOFT START CIRCUIT.
4-34.
The Soft Start circuit consists of the RC network formed by resistor R7 and capacitor C4. The function
of the circuit is to bring the load Voltage up to the required level, slowly enough to avoid large inrush currents.
The output of the Summing Amplifier circuit charges capacitor C4 through resistor R7. If the unit is turned on
when a full load condition exists, the RC network brings the power up to full load smoothly in approximately
200 milliseconds (0.2 seconds).
4-35.
SOFT START RESET CIRCUIT.
4-36.
The Soft Start Reset circuit consists of transistor Q7, resistors R25 through R27, diode D12, and
capacitor C15. When a momentary line drop is detected, the circuit discharges capacitor C4 in the Soft Start
circuit. This action disables the SCR Firing circuits from generating gating pulses. During normal operation,
transistor Q7 is cutoff by the Voltage supplied through resistor R27 from capacitor C15. When the line drops
momentarily, the cutoff Voltage is removed and transistor Q7 turns on rapidly via the bias provided by the +12
V dc regulated supply. When transistor Q7 turns on, capacitor C4 is discharged. At this point, the Soft Start
circuit has been reset. When the line returns to normal, the operation of the Soft Start circuit will be as
described in paragraph 4-34.
4-37.
SCR FIRING CIRCUIT.
The SCR Firing circuit consists of transistor Q6, unijunction transistor (UJT) Q3, zener diodes DZ1 and DZ4,
rectifiers D5 through D8, diode D9, capacitors C6 and C7, resistors R10 through R13 and R49, the primary
winding of pulse transformer T3, and the b secondary winding of power transformer T1. The function of the
circuit is to time the SCR gate trigger pulses in order to control the output power of the unit to the load. The
Voltage across capacitor c4 in the Soft Start circuit varies according to the requirements for obtaining and
maintaining a certain power output. As this Voltage changes, the emitter-base junction Voltage of transistor
Q6 changes. This Voltage controls the collector current of transistor Q6 and thus the charging rate of
capacitor C6. When the Voltage across capacitor C6 reaches the threshold Voltage of UJT Q3, Q3 fires,
suddenly discharging capacitor C6 through UJT Q3 and the primary winding of pulse transformer T3. This
signal is coupled to the Pulse Shaper circuits by the two secondary windings of pulse transformer T3. The
sequence of the operation described above is synchronized to the line by the full wave bridge rectifier formed
by rectifiers D5 through D8. Zener diode DZ4 clips the output of the full wave bridge rectifier to +12 V dc. At a
zero point in the full wave rectified waveform, the Voltage across UJT Q3 is zero, forcing the capacitor C6 to
be discharged. In the next few milliseconds, the Voltage across UJT Q3 jumps to +12 V dc (clipping level of
zener diode DZ4) and the threshold of UJT Q3 becomes approximately +7 V dc. The timing interval now
starts. The faster capacitor C6 charges, the faster the first pulse is generated after the waveform across UJT
Q3 is zero.
4-38.
PULSE SHAPER CIRCUITS.
4-39.
There are two basically identical Pulse Shaper circuits, one for each of the two Power SCR circuits.
The Pulse shaper circuit for Power SCR Q2 consists of silicon controlled rectifier (SCR) Q5, capacitors C9,
C11, and C17, resistors R21 and R22, the e secondary winding of power transformer T1, and a secondary
winding of pulse transformer T3. The Pulse Shaper circuit for Power SCR Q1 consists of SCR Q4, capacitors
C8, C10, and C16, resistors R18 and R20, the d secondary winding of power transformer T1, and the other
secondary winding of pulse transformer T3. The slave SCR's (Q4 and Q5) provide the shaped gate signals for
the Power SCR's. The pulse generated by unijunction transistor (UJT) Q3, in the SCR Firing circuit, is applied
through the secondary winding of pulse transformer T3 to the gate terminals of SCR's Q4 and Q5. The e and
d secondary windings of power transformer T1 are connected such that when SCR Q5 is forward biased, SCR
Q4 is reverse biased. The forward biased SCR (Q5 in this case0 will fire. The steep Voltage rise at the
cathode of SCR Q5 is coupled instantaneously, by capacitor C9, to the gate of Power SCR Q2. Capacitor C9
rapidly charges and the transient Voltage at the gate of SCR Q5 drops to a level determined by resistor R22
and the gate resistance of Power SCR Q2. The gate signal continues until an AC zero is reached on the line
and the SCR Q5 turns off. On the next half cycle, SCR Q4 will fire, and the operation of the Pulse Shaper
28
AMETEK HDR Power Systems
Phase/AMP Series DPA1/DCPA1
Document 9100030
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