Advantech PCE-3032 User Manual page 102

Lga1200 intel xeon, core i9/ i7/i5/i3/celeron/pentium picmg 1.3 half-size system host board with vga/dvi-d/ddr4/ sata3.0/usb3.2/dual gbe
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C.1
Supported GPIO Register
Below are the detailed descriptions of the GPIO addresses and a programming sam-
ple.
C.2
GPIO Registers
Bank
Offset
09h
30h
07h
E0h
07h
E1h
07h
E2h
C.3
GPIO Example Program-1
------------------------------------------------
Enter the extended function mode, interruptible double-write
------------------------------------------------
MOV DX,2EH
MOV AL,87H
OUT DX,AL
OUT DX,AL
---------------------------------------------------------------
Configure logical device, configuration register CRE0,CRE1,CRE2
---------------------------------------------------------------
MOV DX,2EH
MOV AL,09H
OUT DX,AC
DEC DX
MOV AL,30H
OUT DX,AL
INC DX
IN AL,DX
OR AL,10000000B
DEC DX
MOV AL,07H
OUT DX,AL
INC DX
MOV AL,07H ; Select logical device 7
PCE-3032/4132 User Manual
Description
Write 1 to bit 7 to enable GPIO
GPIO I/O Register
When set to a '1', respective GPIO port is programmed as an input port.
When set to a '0', respective GPIO port is programmed as an output port.
GPIO Data Redister
If a port is programmed to be an output port, then its respective bit can be
read/written.
If a port is programmed to be an input port, then its respective bit can only
be read.
GPIO Inversion Register
When set to a '1', the incoming/outgoing port value is inverted.
When set to a '0', the incoming/outgoing port value is the same as in data
register.
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