Board Layout; Layout; Top Layer Pcb Layout - Texas Instruments SoundPlus OPA1622EVM User Manual

Board Layout

5 Board Layout
This section provides a description of the OPA1622EVM board layout and layer illustrations.
5.1

Layout

The board layout for the OPA1622EVM is shown in
signal traces and is poured with a solid ground plane. The traces of the positive input (IN+) and negative
input (IN–) for both the left and right channel were kept as balanced as possible to eliminate any
impedance mismatch due to trace impedance. The decoupling capacitors, C5 and C6, were positioned as
close as possible to the power supply pins of the device. Vias were placed at the ground connection of
every component to provide a low impedance path on the bottom layer back to the supply ground. It is
important to provide a very clean, low impedance return path for the audio jack (J2); therefore multiple
stitching vias were placed around the ground connection of the audio jack. Also, the connection to the
thermal pad of the OPA1622 on the bottom layer was kept to a minimum to ensure currents from the
audio jack ground to the supply ground have a clean return path. Note that due to the size of the copper
pour for the thermal pad on the bottom layer, the thermal performance specified in the OPA1622
datasheet may not be met on the OPA1622EVM. Refer to the application report, PowerPAD™ Thermally
Enhanced Package (SLMA002), for more information.
10
OPA1622EVM SoundPlus™ Audio Operational Amplifier Evaluation Module
Figure 11
Figure 11. Top Layer PCB Layout
Copyright © 2016, Texas Instruments Incorporated
and Figure 12. The top layer consists of all
SBOU172 – September 2016
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