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Holtek HT49RA0 Manual page 16

Remote type 8-bit mcu with lcd

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Input/Output Ports
There are an 8-bit bidirectional input/output port, a 8-bit in-
put port and one-bit input/output port in the
HT49RA0/HT49CA0, labeled as PA, PB and PC which
are mapped to [12H], [14H], [16H] of the RAM respec-
tively. Each bit of PA can be selected as NMOS output or
Schmitt trigger with pull-high resistor by software instruc-
tion. PB0~PB7 can only be used for input operation
(Schmitt trigger with pull-high resistors). PC is only one-bit
input/output port shares the pin with carrier output.
When PA, PB and PC for the input operation, these
ports are non-latched, that is, the inputs should be ready
at the T2 rising edge of the instruction ²MOV A, [m]²
(m=12H or 14H). For PA and PC output operation, all
data are latched and remain unchanged until the output
latch is rewritten.
When the PA is used for input operation, it should be
noted that before reading data from pads, a ²1² should
be written to the related bits to disable the NMOS de-
vice. That is, the instruction ²SET [m].i² (i=0~7 for PA) is
D a t a B u s
C h i p R e s e t
R e a d I / O
S y s t e m
I N T 0 f o r P B 0
I N T 1 f o r P B 1
T M R f o r P B 2
Rev. 1.50
D
Q
W r i t e
C K
Q
S
PA Input/Output Ports
D a t a B u s
R e a d I / O
W a k e - u p
W a k e - u p O p t i o n
PB Input Ports
16
HT49RA0/HT49CA0
executed first to disable related NMOS device, and then
²MOV A, [m]² to get stable data.
After chip reset, PA, PB and PC remain at a high level in-
put line.
Each bit of PA and PC output latches can be set or
cleared by the ²SET [m].i² and ²CLR [m].i² (m=12H or
16H) instructions respectively.
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR [m]²,
²CPL [m]², ²CPLA [m]² read the entire port states into
the CPU, execute the defined operations (bit-operation),
and then write the results back to the latches or to the
accumulator.
Each line of PB has a wake-up capability to the device
by code option. The highest seven bits of PC are not
physically implemented, on reading them a ²0² is re-
turned and writing results in a no-operation.
V
D D
W e a k
P u l l - u p
P A 0 ~ P A 7
V
D D
W e a k
P u l l - u p
P B 0 ~ P B 7
March 20, 2014

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