Holtek HT49RA0 Manual page 14

Timer/Event Counter
One timer/event counters are implemented in the devices.
It contains an 8-bit programmable count-up counter.
The timer/event counter clock source may come from
the system clock or system clock/4 or RTC time-out sig-
nal or external source. System clock source or system
clock/4 is selected by option.
Using external clock input allows the user to count exter-
nal events, measure time internals or pulse widths, or
generate an accurate time base. While using the inter-
nal clock allows the user to generate an accurate time
base.
There are two registers related to the timer/event coun-
ter, i.e., TMR (0DH) and TMRC (0EH). There are also
two physical registers are mapped to TMR location; writ-
ing TMR places the starting value in the timer/event
counter preload register, while reading it yields the con-
tents of the timer/event counter. TMRC is timer/event
counter control register used to define some options.
The TM0 and TM1 bits define the operation mode. The
event count mode is used to count external events,
which means that the clock source is from an external
(TMR) pin. The timer mode functions as a normal timer
with the clock source coming from the internal selected
clock source. Finally, the pulse width measurement
Bit No. Label
¾ Unused bit, read as ²0²
0~2
To define the TMR active edge of timer/event counter
3 TE
(0=active on low to high; 1=active on high to low)
To enable/disable timer counting
4 TON
(0=disabled; 1=enabled)
2 to 1 multiplexer control inputs to select the timer/event counter clock source
5 TS
(0=RTC outputs; 1= system clock or system clock/4)
To define the operating mode (TM1, TM0)
01=Event count mode (External clock)
6 TM0
10=Timer mode (Internal clock)
7 TM1
11=Pulse Width measurement mode (External clock)
00=Unused
S y s t e m C l o c k
O p t i o n
S e l e c t
S y s t e m C l o c k / 4
R T C I n t e r r u p t
Rev. 1.50
TMRC (0EH) Register
M
U
X
T M 1
T S
T M 0
T M R
T E
P u l s e W i d t h
T M 1
M e a s u r e m e n t
T M 0
M o d e C o n t r o l
T O N
Timer/Event Counter
14
HT49RA0/HT49CA0
mode can be used to count the high or low level duration
of the external signal (TMR), and the counting is based
on the internal selected clock source.
In the event count or timer mode, the timer/event coun-
ter starts counting at the current contents in the
timer/event counter and ends at FFH. Once an overflow
occurs, the counter is reloaded from the timer/event
counter preload register, and generates an interrupt re-
quest flag (TF;bit 6 of INTC0).
In the pulse width measurement mode with the val-
ues of the TON and TE bit equal to one, after the TMR
has received a transient from low to high (or high to
low if the TE bit is ²0²), it will start counting until the
TMR returns to the original level and resets the TON.
The measured result remains in the timer/event
counter even if the activated transient occurs again.
In other words, only one cycle measurement can be
made until the TON is set. The cycle measurement will
re-function as long as it receives further transient pulse.
In this operation mode, the timer/event counter begins
counting according not to the logic level but to the tran-
sient edges. In the case of counter overflows, the counter
is reloaded from the timer/event counter preload register
and issues an interrupt request, as in the other two
modes, i.e., event and timer modes.
Function
T i m e r / E v e n t C o u n t e r
P r e l o a d R e g i s t e r
T i m e r / E v e n t
C o u n t e r
D a t a b u s
R e l o a d
O v e r f l o w
T o I n t e r r u p t
March 20, 2014