Holtek HT49RA0 Manual page 11

Watchdog Timer - WDT
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator) or an instruction clock
(system clock/4) or a real time clock oscillator (RTC os-
cillator). The timer is designed to prevent a software
malfunction or sequence from jumping to an unknown
location with unpredictable results. The WDT can be
disabled by option. But if the WDT is disabled, all execu-
tions related to the WDT lead to no operation.
The WDT time-out period is as f
If the WDT clock source chooses the internal WDT oscilla-
tor, the time-out period may vary with temperature, VDD,
and process variations. On the other hand, if the clock
source selects the instruction clock and the ²HALT² in-
struction is executed, WDT may stop counting and lose its
protecting purpose, and the logic can only be restarted by
an external logic.
When the device operates in a noisy environment, using
the on-chip RC oscillator (WDT OSC) is strongly recom-
mended, since the HALT can stop the system clock.
The WDT overflow under normal operation initializes a
²chip reset² and sets the status bit ²TO². In the HALT
mode, the overflow initializes a ²warm reset², and only
the program counter and stack pointer are reset to zero.
To clear the contents of the WDT, there are three meth-
ods to be adopted, i.e., external reset (a low level to
RES), software instruction, and a ²HALT² instruction.
There are two types of software instructions; ²CLR
WDT² and the other set - ²CLR WDT1² and ²CLR
WDT2². Of these two types of instruction, only one type
of instruction can be active at a time depending on the
options - ²CLR WDT² times selection option. If the ²CLR
WDT² is selected (i.e., CLR WDT times equal one), any
execution of the ²CLR WDT² instruction clears the WDT.
In the case that ²CLR WDT1² and ²CLR WDT2² are
chosen (i.e., CLR WDT times equal two), these two in-
structions have to be executed to clear the WDT; other-
wise, the WDT may reset the chip due to time-out.
Time Base
The time base offers a periodic time-out period to gener-
ate a regular internal interrupt. Its time-out period
12 15
ranges from f /2 to f /2 selected by options. If time
S S
base time-out occurs, the related interrupt request flag
S y s t e m C l o c k / 4
R T C
O p t i o n
3 2 7 6 8 H z
O S C
S e l e c t
W D T
1 2 k H z
O S C
Rev. 1.50
16 15
/2 ~f /2 .
S S
f
S
D i v i d e r P r e s c a l e r
Watchdog Timer
11
HT49RA0/HT49CA0
(TBF; bit 4 of INTC1) is set. But if the interrupt is en-
abled, and the stack is not full, a subroutine call to loca-
tion 10H occurs.
f
S
D i v i d e r
O p t i o n
2
L C D D r i v e r ( f / 2 ~ f / 2
S S
2 9
B u z z e r ( f / 2 ~ f / 2 )
S S
Time Base
Real Time Clock - RTC
The real time clock (RTC) is operated in the same man-
ner as the time base that is used to supply a regular inter-
nal interrupt. Its time-out period ranges from f
15
f /2 by software programming . Writing data to RT2,
S
RT1 and RT0 (bit2, 1, 0 of RTCC;09H) yields various
time-out periods. If the RTC time-out occurs, the related
interrupt request flag (RTF; bit 5 of INTC1) is set. But if
the interrupt is enabled, and the stack is not full, a subrou-
tine call to location 14H occurs. The real time clock
time-out signal also can be applied to be a clock source of
Timer/Event Counter for getting a longer time-out period.
RT2 RT1 RT0 RTC Clock Divided Factor
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Note: ²*² not recommended to be used
f
S
D i v i d e r P r e s c a l e r
R T 2
8 t o 1
R T 1
M u x .
R T 0
Real Time Clock
C K T C K
R
W D T C l e a r
P r e s c a l e r
O p t i o n
8
T i m e B a s e I n t e r r u p t
)
1 2 1 5
( f / 2 ~ f / 2 )
S S
8
/2 to
S
8*
2
9*
2
10*
2
11*
2
12
2
13
2
14
2
15
2
8 1 5
f / 2 ~ f / 2
S S
R T C I n t e r r u p t
T
T i m e - o u t R e s e t
1 6 1 5
f / 2 ~ f / 2
R
S S
March 20, 2014