Atmel AT32UC3A3256S Manual page 689

32-bit avr microcontroller

Table of Contents

Device Global Interrupt Register

Access Type:

Reset Value:

• DMAnINT: DMA Channel n Interrupt

This bit is set when an interrupt is triggered by the DMA channel n. This triggers a USB interrupt if DMAnINTE is one.

This bit is cleared when the UDDMAnSTATUS interrupt source is cleared.

• EPnINT: Endpoint n Interrupt

This bit is set when an interrupt is triggered by the endpoint n (UESTAn, UECONn). This triggers a USB interrupt if EPnINTE is

This bit is cleared when the interrupt source is serviced.

• UPRSM: Upstream Resume Interrupt

This bit is set when the USBB sends a resume signal called "Upstream Resume". This triggers a USB interrupt if UPRSME is

This bit is cleared when the UDINTCLR.UPRSMC bit is written to one to acknowledge the interrupt (USB clock inputs must be

enabled before).

• EORSM: End of Resume Interrupt

This bit is set when the USBB detects a valid "End of Resume" signal initiated by the host. This triggers a USB interrupt if

EORSME is one.

This bit is cleared when the UDINTCLR.EORSMC bit is written to one to acknowledge the interrupt.

• WAKEUP: Wake-Up Interrupt

This bit is set when the USBB is reactivated by a filtered non-idle signal from the lines (not by an upstream resume). This

triggers an interrupt if WAKEUPE is one.

This bit is cleared when the UDINTCLR.WAKEUPC bit is written to one to acknowledge the interrupt (USB clock inputs must be

enabled before).

This bit is cleared when the Suspend (SUSP) interrupt bit is set.

This interrupt is generated even if the clock is frozen by the FRZCLK bit.

• EORST: End of Reset Interrupt

This bit is set when a USB "End of Reset" has been detected. This triggers a USB interrupt if EORSTE is one.

This bit is cleared when the UDINTCLR.EORSTC bit is written to one to acknowledge the interrupt.

32072H–AVR32–10/2012

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