Analog Devices ADMV8913-EVALZ User Manual page 7

ADMV8913-EVALZ
Label Function
B Use the SFL Settings section to configure the SPI fast latch settings on the chip when in the SFL mode. Refer to the
data sheet for more information regarding the internal state machine and SFL mode functionality. This section includes the
following:
FAST_LATCH_STATE: this value is the next state of the internal state machine pointer (read only).
FAST_LATCH_START: this value determines the start location within the internal state machine.
FAST_LATCH_STOP: this value determines the stop location within the internal state machine.
FAST_LATCH_DIRECTION: this bit determines the direction that the internal state machine advances for each rising edge of
the CS pin when in SFL mode.
C The Status section includes the following:
Mode: when the SFL pin is low, the mode is SPI Write. When the SFL pin is high, the mode is SPI Fast Latch, and the chip uses
the LUT.
CSB_AUX Count: when in SFL mode, this field displays the number of times the
Message: upon entering SFL mode, the Message field displays Waiting for CSB. Once the CSB_AUX pin is toggled, the
Message field displays the current LUT number followed by the next LUT number.
D The displayed block diagram section shows the actively selected WR or LUT number. This section includes the following:
Displaying Filter States in WR or Displaying Filter States in LUT: the title updates to show the actively selected WR or LUT number.
Displayed States: the HPF state and LPF state populates into the appropriate block.
E The Filter Settings section shows the filter states for the actively selected WR or LUT number. This section includes the following:
HPF State: scroll up or down to set the desired HPF state value (0 to 15).
LPF State: scroll up or down to set the desired LPF state value (0 to 15).
F The Display section determines the actively selected WR or LUT number. This section includes the following:
Mode: use the dropdown menu to select either WR or LUT display mode. When the mode is set to WR, the WR register can be
configured in the Filter Settings section and is displayed on the diagram.
LUT: when the Mode is set to LUT, scroll up and down to set the LUT number (0 to 127) that is currently being configured and
displayed in the Filter Settings section. Changing to the LUT number automatically changes the Mode to LUT.
G Use the Logic Pins section to toggle the
includes the following:
RSTB: clear the check box to bring the ADMV8913 RST pin low, which holds the chip in reset. Select the check box again to
bring the chip out of reset.
SFL: select the check box to bring the ADMV8913 SFL pin high, which places the chip in SFL mode. This action also toggles the
on-board
connected to the SDP-S logic pin, CSB_AUX, and normal SPI transactions are disallowed.
CSB_AUX: this pin is only available in SFL mode. Selecting the check box brings the SDP-S logic pin, CSB_AUX, high, which
advances the internal state machine pointer to the next LUT. If an external waveform generator is connected to the CSB_EXT
port on the ADMV8913-EVALZ, the CSB_AUX pin has no effect, and the CSB_EXT port takes precedence.
H Click Proceed to Memory Map to open the ADMV8913 Memory Map (see Figure 8).
J1 All changes, except within the CONFIGURATION section, do not take effect until clicking Apply Changes. If Auto Apply is highlighted
in the ADMV8913 Board tab (see Figure 5), the Apply Changes feature continuously runs every few seconds, and Apply Changes
does not need clicking to apply or read back the block diagram settings.
To read back all of the SPI registers of the chip, click Read All.
J2
J3 Click Reset Chip to reset the chip.
J4 Click Diff to show registers that are different on the chip.
J5 Click Software Defaults to restore the software defaults to the chip, and then click Apply Changes. The software defaults for
the ADMV8913 is for all writable registers to be zero, except for Register 0x011, which is set to 0x7F. The read only registers
(Register 0x03 to Register 0x05) retain their nominal values.
J6 Click Memory Map Side-By-Side to enable the side-by-side memory map view.
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Evaluation Board User Guide
SDP-S
ADG749BKSZ switch connected to the ADMV8913 CS pin (see Figure 10). While in SFL mode, the ADMV8913 CS pin is
logic pins, which are connected to the logic pins on the ADMV8913 chip. This section
Rev. 0 | Page 7 of 17
SDP-S logic pin, CSB_AUX, was toggled.
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ADMV8913